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TSB41BA3D

www.ti.com

............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009

IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER

2345

• Fully Supports Provisions of IEEE 1394b-2002 • Data Interface to Link-Layer Controller

at S100, S100B, S200, S200B, S400, and S400B Terminal-Selectable From 1394a-2000 Mode

Signaling Rates (B Signifies IEEE 1394b (2/4/8 Parallel Bits at 49.152 MHz) or 1394b

Signaling) Mode (Eight Parallel Bits at 98.304 MHz)

• Fully Supports Provisions of IEEE 1394a-2000 • Interoperable With Link-Layer Controllers

and 1394-1995 Standards for Using 3.3-V Supplies

High-Performance Serial Bus

• Interoperable With Other 1394 Physical Layers

• Fully Interoperable With Firewire™, DTVLink, (PHYs) Using 1.8-V, 3.3-V, and 5-V Supplies

SB1394, DishWire, and i.LINK™

• Low-Cost 49.152-MHz Crystal Provides

Implementation of IEEE Std 1394

Transmit and Receive Data at 100/200/400

• Provides Three Fully Backward-Compatible, Mbps and Link-Layer Controller Clock at

(1394a-2000 Fully Compliant) Bilingual 1394b 49.152 MHz and 98.304 MHz

Cable Ports at 400 Megabits per Second

• Separate Bias (TPBIAS) for Each Port

(Mbps)

• Low-Cost, High-Performance 80-Terminal

• Same Three Fully Backward-Compatible Ports

TQFP (PFP) Thermally Enhanced Package

Are 1394a-2000 Fully Compliant Cable Ports at

• Software Device Reset (SWR)

100/200/400 Mbps

• Fail-Safe Circuitry Senses Sudden Loss of

• Full 1394a-2000 Support Includes:

Power to the Device and Disables the Ports to

– Connection Debounce

Ensure That the TSB41BA3D Does Not Load

– Arbitrated Short Reset the TPBIAS of Any Connected Device and

Blocks Any Leakage From the Port Back to

– Multispeed Concatenation

Power Plane

– Arbitration Acceleration

• 1394a-2000-Compliant, Common-Mode Noise

– Fly-By Concatenation

Filter on the Incoming Bias Detect Circuit to

– Port Disable/Suspend/Resume

Filter Out Crosstalk Noise

– Extended Resume Signaling for

• Cable/Transceiver Hardware Speed and Port

Compatibility With Legacy DV Devices

Mode Are Selectable by Terminal States

• Power-Down Features to Conserve Energy in

• Supports Connection to CAT5 Cable

Battery-Powered Applications

Transceiver by Allowing Ports to be Forced to

• Low-Power Automotive Sleep Mode Support

Beta-Only, 400-Mbps-Only, 200-Mbps-Only or

• Fully Compliant With Open Host Controller 100-Mbps-Only

Interface (OHCI) Requirements

• Supports Connection to S200 Plastic Optical

• Cable Power Presence Monitoring Fiber Transceivers by Allowing Ports to be

Forced to 1394b Beta-Only, S200-Mbps-Only,

• Cable Ports Monitor Line Conditions for Active

and S100-Mbps-Only

Connection to Remote Node

• Optical Signal Detect Input for All Ports in

• Register Bits Give Software Control of

Beta Mode Enables Connection to Optical

Contender Bit, Power Class Bits, Link Active

Transceivers

Control Bit, and 1394a-2000 Features

• Supports Use of 1394a Connectors by

• Interface to Link-Layer Controller Supports

Allowing Ports 1 and 2 to Be Forced to

Low-Cost TI Bus-Holder Isolation

1394a-Only Mode

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 PowerPAD is a trademark of Texas Instruments.

3 Firewire is a trademark of Apple Computer, Inc.

4 i.LINK is a trademark of Sony Kabushiki Kaisha TA Sony Corporation.

5 All other trademarks are the property of their respective owners.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (59 pages)

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TSB41BA3D www.ti.com ...............................................................................................................................................
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com DESCRIPTION/ORDERING INFORMATION The TSB41BA3D provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 NOTE: The BMODE terminal does not select the cable interface mode of operation. The BMODE terminal selects the PHY-link interface mode of operation and affects the arbitration modes on the cable.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com NOTE: A bilingual port can only connect to a 1394b-only port that operates at S400b. It cannot establish a connection to a S200b or S100b port. A port that has been forced to S400b (B4) can connect to a 1394b-only port at S400b (B4) or S200b (B2) or S100b (B1).
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TSB41BA3D www.ti.com ...............................................................................................................................................
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 1. Terminal Functions TERMINAL NAME TYPE PFP NO. I/O DESCRIPTION AGND Supply 21, 40, 43, 50, 61, 62 – Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 1. Terminal Functions (continued) TERMINAL NAME LCLK_PMC TYPE CMOS PFP NO. I/O DESCRIPTION 7 I Link clock. Link-provided 98.304-MHz clock signal to synchronize data transfers from link to the PHY.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 1. Terminal Functions (continued) TERMINAL NAME TYPE PFP NO. I/O DESCRIPTION PLLGND Supply 25, 28 – PLL circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. PLLVDD-CORE Supply 29, 30 – PLL core circuit power terminals.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 1. Terminal Functions (continued) TERMINAL NAME TYPE PFP NO. I/O DESCRIPTION Port sleep/mode selection terminal 5 and link-on output. This terminal can be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 1. Terminal Functions (continued) TERMINAL NAME XI XO TYPE Crystal PFP NO. I/O DESCRIPTION 27 26 I O Crystal oscillator inputs. These terminals connect to a 49.152-MHz parallel-resonant fundamental-mode crystal.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 2. Port Speed/Mode Selection INPUT SELECTION MOD E NO.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 PORT MODE/SPEED SELECTION EXAMPLE CONNECTIONS 3.3 V TSB41BA3D 3.3 V Signal Detect PC0 (Don’t Care) S5 TPBIAS0_SD0 S4 Port 0 S3 TPBIAS1_SD1 S2_PC0 Port 1 S1_PC1 TPBIAS2_SD2 S0_PC2 Port 2 POF S200 TPBIAS 1394b 9-Pin Bilingual 3.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com ABSOLUTE MAXIMUM RATINGS (1) over operating free-air temperature (unless otherwise noted) MIN MAX VDD Supply voltage range (2) –0.3 4 V VI Input voltage range (2) –0.5 VDD + 0.5 V VO Output voltage range at any output –0.5 VDD + 0.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 RECOMMENDED OPERATING CONDITIONS Supply voltage, 3.3 VDD Supply voltage, 1.8 VDD Source power node TYP (1) MAX 3 3.3 3.6 Nonsource power node 3 (2) 3.3 3.6 TSB41BA3D 1.7 1.85 2 TSB41BA3DI 1.75 1.85 2 LREQ, CTL0, CTL1, D0–D7, LCLK_PMC High-level input voltage, VIH MIN 0.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com ELECTRICAL CHARACTERISTICS Driver over recommended ranges of operating conditions (unless otherwise noted) PARAMETER TEST CONDITION MAX UNIT 265 mV 800 mV –1.05 (1) 1.05 (1) mA S200 speed signaling enabled –4.84 (2) –2.
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TSB41BA3D www.ti.com ...............................................................................................................................................
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com PARAMETER MEASUREMENT INFORMATION TPAx+ TPBx+ 56 Ω TPAxTPBx- Figure 1. Test Load Diagram xCLK tsu th Dx, CTLx, LREQ Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms xCLK td Dx, CTLx Figure 3.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 APPLICATION INFORMATION Obtain reference schematics, reference layouts, debug documents, and software recommendations for the TSB41BA3D from the Texas Instruments website or your local Texas Instruments representative.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 5. Base Register Field Descriptions (continued) FIELD SIZE TYPE DESCRIPTION Num_Ports 4 Rd Number of ports. This field indicates the number of ports implemented in the PHY. For the TSB41BA3D, this field is 3. PHY_Speed 3 Rd PHY speed capability. This field is no longer used.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 5. Base Register Field Descriptions (continued) FIELD SIZE TYPE DESCRIPTION STOI 1 Rd/Wr State time-out interrupt. This bit indicates that a state time-out has occurred (which also causes a bus reset to occur).
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 7. Page 0 (Port Status) Register Field Descriptions FIELD Astat SIZE 2 TYPE Rd DESCRIPTION TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows: Code Arb Value 11 01 10 00 Z 1 0 invalid Bstat 2 Rd TPB line state.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 7. Page 0 (Port Status) Register Field Descriptions (continued) FIELD SIZE TYPE DESCRIPTION Max_port_speed 3 Rd/Wr Max_port_speed The maximum speed at which a port is allowed to operate in Beta mode.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 8. Page 1 (Vendor ID) Register Configuration BIT POSITION Address 0 1 2 3 1000 4 5 6 7 Compliance 1001 Reserved 1010 Vendor_ID0 1011 Vendor_ID1 1100 Vendor_ID2 1101 Product_ID0 1110 Product_ID1 1111 Product_ID2 Table 9.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 12. Power-Class Descriptions PC0–PC2 DESCRIPTION 000 Node does not need power and does not repeat power. 001 Node is self-powered and provides a minimum of 15 W to the bus. 010 Node is self-powered and provides a minimum of 30 W to the bus.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Outer Cable Shield 0.01 µF 1 MΩ 0.001 µF Chassis Ground Figure 5. Typical DC-Isolated Outer Shield Termination Outer Cable Shield Chassis Ground Figure 6. Non-DC-Isolated Outer Shield Termination 10 kΩ Link Power LPS Square-Wave Input LPS 10 kΩ Figure 7.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Designing With PowerPAD™ Devices The TSB41BA3D is housed in a high-performance, thermally enhanced, 80-terminal PFP PowerPAD package.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com The TSB41BA3D also functions with an LLC that is compliant with the older 1394 standards.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Crystal Selection The TSB41BA3D and other Texas Instruments PHY devices are designed to use an external 49.152-MHz crystal connected between the XI and XO terminals to provide the reference for an internal oscillator circuit.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com C9 X1 IS X1 49.152 MHz CPHY + CBD X0 C10 Figure 10.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 It is recommended that the RHB and gap-count register only be updated by PHY configuration packets.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com PRINCIPLES OF OPERATION (1394a-2000 INTERFACE) The TSB41BA3D is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 13 and Table 14 show the encoding of the CTL0–CTL1 bus. Table 13.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 16 shows the encoding for the request type. Table 16. Request Type Encoding LR1–LR3 NAME DESCRIPTION 000 ImmReq Immediate bus request. On detection of idle, the PHY takes control of the bus immediately without arbitration. 001 IsoReq Isochronous bus request.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 20. Write Register Request BIT(s) 0 NAME DESCRIPTION Start bit Indicates the beginning of the transfer (always 1) 1–3 Request type A 101 indicates this is a write register request.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com The arbitration acceleration enhancements can interfere with the ability of the cycle master node to transmit the cycle start message under certain circumstances.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 a. Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com The PHY asserts at least one idle cycle following a receive operation. SYSCLK CTL0, CTL1 (a) D0–D7 XX 10 00 (b) (c) FF (data-on) 00 Figure 16. Null Packet Reception Timing The sequence of events for a null packet reception is as follows: a. Receive operation initiated.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 When the LLC is ready to send data, the LLC asserts transmit on the CTL terminals as well as sending the first bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com packet speed code is the same as the encoding for the received packet speed code (see Table 23). The link cannot concatenate an S100 packet onto any higher-speed packet. g.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 24. LPS Timing Parameters SYMBOL DESCRIPTION MIN MAX UNIT tLPSL LPS low time (when pulsed) 0.09 2.6 µs tLPSH LPS high time (when pulsed) (1) 0.021 2.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com d. Interface restored. After the minimum tRESTORE time, the LLC can again assert LPS active. When LPS is asserted, the interface is initialized as described in the following paragraph. If the LLC continues to keep the LPS signal deasserted, it then requests that the interface be disabled.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 After the interface has been reset, or reset and then disabled, the interface is initialized and restored to normal operation when LPS is reasserted by the LLC. Figure 21 shows the timing for interface initialization.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com PRINCIPLES OF OPERATION (1394b INTERFACE) The TSB41BA3D is designed to operate with an LLC such as the Texas Instruments TSB82AA2 when the BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 The PHY initiates a transmit operation after winning control of the serial bus following a bus request by the LLC. The transmit operation is initiated when the PHY grants control of the interface to the LLC. Table 25 and Table 26 show the encoding of the CTL0–CTL1 bus. Table 25.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 28 shows the encoding for the request type. Table 28. Request Type Encoding LR1–LR4 NAME DESCRIPTION 0000 Reserved Reserved 0001 Immed_Req Immediate request. On detection of idle, the PHY arbitrates for the bus. 0010 Next_Even Next even request.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 31. Bus Request Speed Encoding LR6–LR9 DATA RATE 0000 S100 0001 Reserved 0010 S200 0011 Reserved 0100 S400 0101 Reserved 0110 S800 All Others Invalid NOTE: The TSB41BA3D accepts a bus request with an invalid speed code and processes the bus request normally.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com To send an acknowledge packet, the LLC must issue an immediate bus request (Immed_Req) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 PHY status transfers use the PINT terminal to send status information serially to the LLC as shown in Figure 25. PHY status transfers (see Table 36) can occur at any time during normal operation.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com The PHY can optionally send status information to the LLC at anytime during the data-on indication. Only bus status transfer information can be sent during a data-on indication.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 d. Receive data. Following the data-on indication (if any) and the speed code, the PHY asserts packet data on the D lines with receive on the CTL lines for the remainder of the receive operation. e. Receive operation terminated.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com bits of packet data on the D lines. The transmit state is held on the CTL terminals until the last bits of data have been sent. The LLC then asserts either hold or idle on the CTL terminals for one clock cycle.
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TSB41BA3D www.ti.com ............................................................................................................................................... SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 Table 39. Link Request Type Encoding During Packet Transmission D1–D3 Request Type 000 No request 001 Isoch_Req_Odd 010 Isoch_Req_Even 011 Current 100 Next_Even 101 Next_Odd 110 Cyc_Start_Req 111 Reserved Table 40.
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TSB41BA3D SLLS959A – DECEMBER 2008 – REVISED MARCH 2009 ............................................................................................................................................... www.ti.com Table 44. Grant Type Values During Grant Cycle [D1–D3] VALUE DURING GRANT CYCLE REQUEST TYPE 000 Reserved 001 Reserved 010 Isochronous grant 011 Reserved 100 Reserved 101 Asynchronous grant 110 Cycle start grant 111 Immediate grant Table 45.
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PACKAGE OPTION ADDENDUM www.ti.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.