Data Manual February 2003 1394 Host Controller Solutions SLLS450A
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Contents Section 1 2 3 4 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Documents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Trademarks . . .
5 iv 4.5 CSR Compare Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.6 CSR Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.7 Configuration ROM Header Register . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.8 Bus Identification Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4.9 Bus Options Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
.2 Isochronous Receive Digital Video Enhancements . . . . . . . . . . . . . . . 5–2 5.3 Isochronous Receive Digital Video Enhancements Register . . . . . . . 5–2 5.4 Link Enhancement Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–4 5.5 Timestamp Offset Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5–5 6 Serial EEPROM Interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure 2–1 2–2 3–1 8–1 8–2 8–3 8–4 8–5 9–1 vi Title Page PDT Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–2 PGE Package Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2–3 TSB43AB23 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3–2 TP Cable Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Tables Table 2–1 2–2 2–3 2–4 2–5 2–6 2–7 2–8 2–9 3–1 3–2 3–3 3–4 3–5 3–6 3–7 3–8 3–9 3–10 3–11 3–12 3–13 3–14 3–15 3–16 3–17 3–18 3–19 3–20 3–21 3–22 4–1 4–2 4–3 4–4 4–5 4–6 Title PDT Package Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . PGE Package Signals Sorted by Terminal Number . . . . . . . . . . . . . . . . . . Signal Names Sorted Alphanumerically to Terminal Number . . . . . . . . . . PCI System Terminals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
4–7 4–8 4–9 4–10 4–11 4–12 4–13 4–14 4–15 4–16 4–17 4–18 4–19 4–20 4–21 4–22 4–23 4–24 4–25 4–26 4–27 4–28 4–29 4–30 4–31 4–32 4–33 4–34 4–35 5–1 5–2 5–3 5–4 6–1 6–2 7–1 7–2 7–3 7–4 7–5 7–6 7–7 7–8 7–9 viii Bus Options Register Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Configuration ROM Mapping Register Description . . . . . . . . . . . . . . . . . . . Posted Write Address Low Register Description . . . . . . . . . . . . . . . . . . . .
1 Introduction This chapter provides an overview of the Texas Instruments TSB43AB23 device and its features. 1.1 Description The Texas Instruments TSB43AB23 device is an integrated 1394a-2000 OHCI PHY/link-layer controller (LLC) device that is fully compliant with the PCI Local Bus Specification, the PCI Bus Power Management Interface Specification (Revision 1.1), IEEE Std 1394-1995, IEEE Std 1394a-2000, and the 1394 Open Host Controller Interface Specification (Release 1.1).
Both the TPA and TPB cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration. The outputs of these comparators are used by the internal logic to determine the arbitration status. The TPA channel monitors the incoming cable common-mode voltage. The value of this common-mode voltage is used during arbitration to set the speed of the next packet transmission.
1.2 Features The TSB43AB23 device supports the following features: • Fully compliant with 1394 Open Host Controller Interface Specification (Release 1.1) • Fully compliant with provisions of IEEE Std 1394-1995 for a high-performance serial bus† and IEEE Std 1394a-2000 • Fully interoperable with FireWire and i.
• PCI power-management D0, D1, D2, and D3 power states • Initial bandwidth available and initial channels available registers • PME support per 1394 Open Host Controller Interface Specification 1.3 Related Documents • 1394 Open Host Controller Interface Specification (Release 1.
2 Terminal Descriptions This section provides the terminal descriptions for the TSB43AB23 device. Figure 2–2 shows the signal assigned to each terminal in the package. Table 2–1 and Table 2–3 provide a cross-reference between each terminal number and the signal name on that terminal. Table 2–1 is arranged in terminal number order, and Table 2–3 lists signals in alphabetical order.
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 TSB43AB23 30 31 32 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 PCI_AD13 PCI_AD12 PCI_AD11 DGND PCI_AD10 PCI_AD9 PCI_AD8 DVDD PCI_C/BE0 PCI_AD7 DGND PCI_AD6 PCI_AD5 VDDP PCI_AD4 PCI_AD3 PCI_AD2 PCI_AD1 DGND PCI_AD0 PCI_RST CYCLEOUT CYCLEIN DVDD GPIO3/TEST1 GPIO2/TEST0 SCL SDA REG18 PC2 PC1 PC0 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60
108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 NC NC TPBIAS2 TPA2+ TPA2– AVDD TPB2+ TPB2– AVDD AGND TPBIAS1 TPA1+ TPA1– AVDD AGND TPB1+ TPB1– AVDD AGND TPBIAS0 TPA0+ TPA0– AGND TPB0+ TPB0– AGND AVDD AGND AVDD CPS PHY_TEST_MA CNA DGND DVDD NC NC PGE PACKAGE (TOP VIEW) 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 TSB43AB23 131 132 133 134 135 136 137 138 139 140 141 142 NC NC PC0 PC1 PC2 REG1
Table 2–1. PDT Package Signals Sorted by Terminal Number NO. 2–4 TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
Table 2–2. PGE Package Signals Sorted by Terminal Number NO. TERMINAL NAME NO. TERMINAL NAME NO. TERMINAL NAME NO.
Table 2–3. Signal Names Sorted Alphanumerically to Terminal Number 2–6 TERMINAL NAME PDT NO. PGE NO. TERMINAL NAME PDT NO. PGENO. TERMINAL NAME PDT NO. PGENO.
The terminals are grouped in tables by functionality, such as PCI system function and power supply function (see Table 2–4 through Table 2–9). The terminal numbers are also listed for convenient reference. Table 2–4. PCI System Terminals TERMINAL NAME PDT NO. PGE NO. I/O DESCRIPTION G_RST 110 124 I Global power reset. This reset brings all of the TSB43AB23 internal registers to their default states, including those registers not reset by PCI_RST.
Table 2–6. PCI Interface Control Terminals TERMINAL NAME PDT NO. PGE NO. I/O DESCRIPTION PCI_CLKRUN 108 122 I/O Clock run. This terminal provides clock control through the CLKRUN protocol. This terminal is implemented as open-drain and must be pulled low through a 10-kΩ nominal resistor for designs where CLKRUN is not implemented. For mobile applications where CLKRUN is implemented, the pullup resistor is typically provided by the system central resource.
Table 2–7. Miscellaneous Terminals TERMINAL NAME CYCLEIN PDT NO. PGE NO. I/O DESCRIPTION 55 61 I/O The CYCLEIN terminal allows an external 8-kHz clock to be used as a cycle timer for synchronization with other system devices. If this terminal is not implemented, it must be pulled high to DVDD through a pullup resistor. CYCLEOUT 54 60 I/O The CYCLEOUT terminal provides an 8-kHz cycle timer synchronization signal.
Table 2–8. Physical Layer Terminals TERMINAL NAME PDT NO. PGE NO. TYPE I/O DESCRIPTION Cable not active. This terminal is asserted high when there are no ports receiving incoming bias voltage. If not used, this terminal must be strapped either to DVDD or to GND through a resistor. To enable the CNA terminal, the BIOS must set bit 7 (CNAOUT) of the PCI PHY control register at offset ECh in the PCI configuration space (see Section 3.20, PCI PHY Control Register).
Table 2–9. Power Supply Terminals TERMINAL NAME AGND PDT NO. PGE NO. 71, 73, 76, 80, 84, 89, 97 81, 83, 86, 90, 94, 99, 111 TYPE I/O DESCRIPTION Supply – Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. AVDD 70, 72, 81, 85, 90, 93, 98 80, 82, 91, 95, 100, 103, 112 Supply – Analog circuit power terminals. A parallel combination of high frequency decoupling capacitors near each terminal is suggested, such as 0.1 µF and 0.
3 TSB43AB23 1394 OHCI Controller Programming Model This section describes the internal PCI configuration registers used to program the TSB43AB23 1394 open host controller interface. All registers are detailed in the same format: a brief description for each register is followed by the register offset and a bit table describing the reset state for each register.
PCI Target SM Internal Registers Serial ROM OHCI PCI Power Mgmt and CLKRUN GPIOs Isochronous Transmit Contexts Asynchronous Transmit Contexts Misc Interface Transmit FIFO Physical DMA and Response Resp Time-out PCI Host Bus Interface Central Arbiter and PCI Initiator SM Link Transmit Receive Acknowledge PHY Register Access and Status Monitor Cycle Start Generator and Cycle Monitor Request Filters Synthesized Bus Reset Link Receive General Request Receive Asynchronous Response Receive PHY/
3.1 PCI Configuration Registers The TSB43AB23 device is a single-function PCI device. The configuration header is compliant with the PCI Local Bus Specification as a standard header. Table 3–2 illustrates the PCI configuration header that includes both the predefined portion of the configuration space and the user-definable registers. Table 3–2.
3.3 Device ID Register The device ID register contains a value assigned to the TSB43AB23 device by Texas Instruments. The device identification for the TSB43AB23 device is 8024h. Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 1 0 0 0 0 0 0 0 Name 8 7 6 5 4 3 2 1 0 R R R R R R R R 0 0 1 0 0 1 0 0 Device ID Register: Offset: Type: Default: Device ID 02h Read-only 8024h 3.
3.5 Status Register The status register provides status over the TSB43AB23 interface to the PCI bus. All bit functions adhere to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 3–4 for a complete description of the register contents.
3.6 Class Code and Revision ID Register The class code and revision ID register categorizes the TSB43AB23 device as a serial bus controller (0Ch), controlling an IEEE 1394 bus (00h), with an OHCI programming model (10h). Furthermore, the TI chip revision is indicated in the least significant byte. See Table 3–5 for a complete description of the register contents.
3.8 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the TSB43AB23 PCI header type and no built-in self-test. See Table 3–7 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Name 8 7 6 5 4 3 2 1 0 Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Offset: Type: Default: Header type and BIST 0Eh Read-only 0000h Table 3–7.
3.10 TI Extension Base Address Register The TI extension base address register is programmed with a base address referencing the memory-mapped TI extension registers. When BIOS writes all 1s to this register, the value read back is FFFF C000h, indicating that at least 16K bytes of memory address space are required for the TI registers. See Table 3–9 for a complete description of the register contents.
3.11 Subsystem Identification Register The subsystem identification register is used for system and option card identification purposes. This register can be initialized from the serial EEPROM or programmed via the subsystem access register at offset F8h in the PCI configuration space (see Section 3.23, Subsystem Access Register). See Table 3–10 for a complete description of the register contents.
3.13 Interrupt Line and Pin Register The interrupt line and pin register communicates interrupt line routing information. See Table 3–11 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 Type R R R R R R R R Default 0 0 0 0 0 0 0 1 Name 8 7 6 5 4 3 2 1 0 R/W R/W R/W R/W R/W R/W R/W R/W 0 0 0 0 0 0 0 0 Interrupt line and pin Register: Offset: Type: Default: Interrupt line and pin 3Ch Read/Write 0100h Table 3–11.
3.15 OHCI Control Register The PCI OHCI control register is defined by the 1394 Open Host Controller Interface Specification and provides a bit for big endian PCI support. See Table 3–13 for a complete description of the register contents.
3.17 Power Management Capabilities Register The power management capabilities register indicates the capabilities of the TSB43AB23 device related to PCI power management. See Table 3–15 for a complete description of the register contents.
3.18 Power Management Control and Status Register The power management control and status register implements the control and status of the PCI power management function. This register is not affected by the internally generated reset caused by the transition from the D3hot to D0 state. See Table 3–16 for a complete description of the register contents.
3.20 PCI PHY Control Register The PCI PHY control register provides a method for enabling the PHY CNA output. See Table 3–18 for a complete description of the register contents.
3.21 Miscellaneous Configuration Register The miscellaneous configuration register provides miscellaneous PCI-related configuration. See Table 3–19 for a complete description of the register contents.
3.22 Link Enhancement Control Register The link enhancement control register implements TI proprietary bits that are initialized by software or by a serial EEPROM, if present. After these bits are set to 1, their functionality is enabled only if bit 22 (aPhyEnhanceEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register) is set to 1. See Table 3–20 for a complete description of the register contents.
Table 3–20. Link Enhancement Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 RSVD R This bit is not assigned in the TSB43AB23 follow-on products, because this bit location loaded by the serial EEPROM from the enhancements field corresponds to bit 23 (programPhyEnable) in the host controller control register at OHCI offset 50h/54h (see Section 4.16, Host Controller Control Register). 5–2 RSVD R Reserved. Bits 5–2 return 0s when read.
3.24 GPIO Control Register The GPIO control register has the control and status bits for the GPIO2 and GPIO3 ports. See Table 3–22 for a complete description of the register contents.
4 OHCI Registers The OHCI registers defined by the 1394 Open Host Controller Interface Specification are memory-mapped into a 2K-byte region of memory pointed to by the OHCI base address register at offset 10h in PCI configuration space (see Section 3.9, OHCI Base Address Register). These registers are the primary interface for controlling the TSB43AB23 IEEE 1394 link function. This section provides the register interface and bit descriptions.
Table 4–1.
Table 4–1.
4.1 OHCI Version Register The OHCI version register indicates the OHCI version support and whether or not the serial EEPROM is present. See Table 4–2 for a complete description of the register contents.
4.2 GUID ROM Register The GUID ROM register accesses the serial EEPROM, and is only applicable if bit 24 (GUID_ROM) in the OHCI version register at OHCI offset 00h (see Section 4.1, OHCI Version Register) is set to 1. See Table 4–3 for a complete description of the register contents.
4.3 Asynchronous Transmit Retries Register The asynchronous transmit retries register indicates the number of times the TSB43AB23 device attempts a retry for asynchronous DMA request transmit and for asynchronous physical and DMA response transmit. See Table 4–4 for a complete description of the register contents.
4.5 CSR Compare Register The CSR compare register accesses the bus management CSR registers from the host through compare-swap operations. This register contains the data to be compared with the existing value of the CSR resource.
4.7 Configuration ROM Header Register The configuration ROM header register externally maps to the first quadlet of the 1394 configuration ROM, offset FFFF F000 0400h. See Table 4–6 for a complete description of the register contents.
4.9 Bus Options Register The bus options register externally maps to the second quadlet of the Bus_Info_Block. See Table 4–7 for a complete description of the register contents.
4.10 GUID High Register The GUID high register represents the upper quadlet in a 64-bit global unique ID (GUID) which maps to the third quadlet in the Bus_Info_Block. This register contains node_vendor_ID and chip_ID_hi fields. This register initializes to 0s on a system (hardware) reset, which is an illegal GUID value. If a serial EEPROM is detected, the contents of this register are loaded through the serial EEPROM interface after a G_RST. At that point, the contents of this register cannot be changed.
4.12 Configuration ROM Mapping Register The configuration ROM mapping register contains the start address within system memory that maps to the start address of 1394 configuration ROM for this node. See Table 4–8 for a complete description of the register contents.
4.14 Posted Write Address High Register The posted write address high register communicates error information if a write request is posted and an error occurs while writing the posted data packet. See Table 4–10 for a complete description of the register contents.
4.16 Host Controller Control Register The host controller control set/clear register pair provides flags for controlling the TSB43AB23 device. See Table 4–11 for a complete description of the register contents.
Table 4–11. Host Controller Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 aPhyEnhanceEnable RSC When bits 23 (programPhyEnable) and 17 (linkEnable) are 1, the OHCI driver can set bit 22 to 1 to use all IEEE 1394a-2000 enhancements. When bit 23 (programPhyEnable) is cleared to 0, the software does not change PHY enhancements or this bit. 21–20 RSVD R 19 LPS RSC Reserved. Bits 21 and 20 return 0s when read. Bit 19 controls the link power status.
4.18 Self-ID Count Register The self-ID count register keeps a count of the number of times the bus self-ID process has occurred, flags self-ID packet errors, and keeps a count of the self-ID data in the self-ID buffer. See Table 4–12 for a complete description of the register contents.
4.19 Isochronous Receive Channel Mask High Register The isochronous receive channel mask high set/clear register enables packet receives from the upper 32 isochronous data channels. A read from either the set register or clear register returns the content of the isochronous receive channel mask high register. See Table 4–13 for a complete description of the register contents.
Table 4–13. Isochronous Receive Channel Mask High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 6 isoChannel38 RSC When bit 6 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 38. 5 isoChannel37 RSC When bit 5 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 37. 4 isoChannel36 RSC When bit 4 is set to 1, the TSB43AB23 device is enabled to receive from isochronous channel number 36.
4.21 Interrupt Event Register The interrupt event set/clear register reflects the state of the various TSB43AB23 interrupt sources. The interrupt bits are set to 1 by an asserting edge of the corresponding interrupt signal or by writing a 1 in the corresponding bit in the set register. The only mechanism to clear a bit in this register is to write a 1 to the corresponding bit in the clear register.
Table 4–15. Interrupt Event Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 22 cycleLost RSCU A lost cycle is indicated when no cycle_start packet is sent or received between two successive cycleSynch events. A lost cycle can be predicted when a cycle_start packet does not immediately follow the first subaction gap after the cycleSynch event or if an arbitration reset gap is detected after a cycleSynch event without an intervening cycle start.
4.22 Interrupt Mask Register The interrupt mask set/clear register enables the various TSB43AB23 interrupt sources. Reads from either the set register or the clear register always return the contents of the interrupt mask register. In all cases except masterIntEnable (bit 31) and vendorSpecific (bit 30), the enables for each interrupt event align with the interrupt event register bits detailed in Table 4–15.
Table 4–16. Interrupt Mask Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 21 cycle64Seconds RSC When this bit and bit 21 (cycle64Seconds) in the interrupt event register at OHCI offset 80h/84h (see Section 4.21, Interrupt Event Register) are set to 1, this 64-second-cycle interrupt mask enables interrupt generation. 20 cycleSynch RSC When this bit and bit 20 (cycleSynch) in the interrupt event register at OHCI offset 80h/84h (see Section 4.
4.23 Isochronous Transmit Interrupt Event Register The isochronous transmit interrupt event set/clear register reflects the interrupt state of the isochronous transmit contexts. An interrupt is generated on behalf of an isochronous transmit context if an OUTPUT_LAST* command completes and its interrupt bits are set to 1. Upon determining that the isochTx (bit 6) interrupt has occurred in the interrupt event register at OHCI offset 80h/84h (see Section 4.
4.24 Isochronous Transmit Interrupt Mask Register The isochronous transmit interrupt mask set/clear register enables the isochTx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous transmit interrupt mask register. In all cases the enables for each interrupt event align with the isochronous transmit interrupt event register bits detailed in Table 4–17.
4.26 Isochronous Receive Interrupt Mask Register The isochronous receive interrupt mask set/clear register enables the isochRx interrupt source on a per-channel basis. Reads from either the set register or the clear register always return the contents of the isochronous receive interrupt mask register. In all cases the enables for each interrupt event align with the isochronous receive interrupt event register bits detailed in Table 4–18.
4.28 Initial Channels Available High Register The initial channels available high register value is loaded into the corresponding bus management CSR register on a system (hardware) or software reset. See Table 4–20 for a complete description of the register contents.
4.30 Fairness Control Register The fairness control register provides a mechanism by which software can direct the host controller to transmit multiple asynchronous requests during a fairness interval. See Table 4–22 for a complete description of the register contents.
4.31 Link Control Register The link control set/clear register provides the control flags that enable and configure the link core protocol portions of the TSB43AB23 device. It contains controls for the receiver and cycle timer. See Table 4–23 for a complete description of the register contents.
4.32 Node Identification Register The node identification register contains the address of the node on which the iOHCI-Lynx chip resides and indicates the valid node number status. The 16-bit combination of the busNumber field (bits 15–6) and the NodeNumber field (bits 5–0) is referred to as the node ID. See Table 4–24 for a complete description of the register contents.
4.33 PHY Layer Control Register The PHY layer control register reads from or writes to a PHY register. See Table 4–25 for a complete description of the register contents.
4.34 Isochronous Cycle Timer Register The isochronous cycle timer register indicates the current cycle number and offset. When the TSB43AB23 device is cycle master, this register is transmitted with the cycle start message. When the TSB43AB23 device is not cycle master, this register is loaded with the data field in an incoming cycle start. In the event that the cycle start message is not received, the fields can continue incrementing on their own (if programmed) to maintain a local time reference.
4.35 Asynchronous Request Filter High Register The asynchronous request filter high set/clear register enables asynchronous receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for either the physical request context or the ARRQ context, the source node ID is examined. If the bit corresponding to the node ID is not set to 1 in this register, the packet is not acknowledged and the request is not queued.
Table 4–27. Asynchronous Request Filter High Register Description (Continued) 4–32 BIT FIELD NAME TYPE DESCRIPTION 18 asynReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, asynchronous requests received by the TSB43AB23 device from that node are accepted. 17 asynReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, asynchronous requests received by the TSB43AB23 device from that node are accepted.
4.36 Asynchronous Request Filter Low Register The asynchronous request filter low set/clear register enables asynchronous receive requests on a per-node basis, and handles the lower node IDs. Other than filtering different node IDs, this register behaves identically to the asynchronous request filter high register. See Table 4–28 for a complete description of the register contents.
4.37 Physical Request Filter High Register The physical request filter high set/clear register enables physical receive requests on a per-node basis, and handles the upper node IDs. When a packet is destined for the physical request context, and the node ID has been compared against the ARRQ registers, then the comparison is done again with this register.
Table 4–29. Physical Request Filter High Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 18 physReqResource50 RSC If bit 18 is set to 1 for local bus node number 50, physical requests received by the TSB43AB23 device from that node are handled through the physical request context. 17 physReqResource49 RSC If bit 17 is set to 1 for local bus node number 49, physical requests received by the TSB43AB23 device from that node are handled through the physical request context.
4.38 Physical Request Filter Low Register The physical request filter low set/clear register enables physical receive requests on a per-node basis, and handles the lower node IDs. When a packet is destined for the physical request context and the node ID has been compared against the asynchronous request filter registers, then the node ID comparison is done again with this register.
4.40 Asynchronous Context Control Register The asynchronous context control set/clear register controls the state and indicates status of the DMA context. See Table 4–31 for a complete description of the register contents.
4.41 Asynchronous Context Command Pointer Register The asynchronous context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB23 device accesses when software enables the context by setting bit 15 (run) in the asynchronous context control register (see Section 4.40, Asynchronous Context Control Register) to 1. See Table 4–32 for a complete description of the register contents.
4.42 Isochronous Transmit Context Control Register The isochronous transmit context control set/clear register controls options, state, and status for the isochronous transmit DMA contexts. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3, …, 7). See Table 4–33 for a complete description of the register contents.
4.43 Isochronous Transmit Context Command Pointer Register The isochronous transmit context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB23 device accesses when software enables an isochronous transmit context by setting bit 15 (run) in the isochronous transmit context control register (see Section 4.42, Isochronous Transmit Context Control Register) to 1. The isochronous transmit DMA context command pointer can be read when a context is active.
Table 4–34. Isochronous Receive Context Control Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 29 cycleMatchEnable RSCU When bit 29 is set to 1 and the 13-bit cycleMatch field (bits 24–12) in the isochronous receive context match register (See Section 4.46, Isochronous Receive Context Match Register) matches the 13-bit cycleCount field in the cycleStart packet, the context begins running. The effects of this bit, however, are impacted by the values of other bits in this register.
4.45 Isochronous Receive Context Command Pointer Register The isochronous receive context command pointer register contains a pointer to the address of the first descriptor block that the TSB43AB23 device accesses when software enables an isochronous receive context by setting bit 15 (run) in the isochronous receive context control register (see Section 4.44, Isochronous Receive Context Control Register) to 1. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3).
4.46 Isochronous Receive Context Match Register The isochronous receive context match register starts an isochronous receive context running on a specified cycle number, filters incoming isochronous packets based on tag values, and waits for packets with a specified synchronous value. The n value in the following register addresses indicates the context number (n = 0, 1, 2, 3). See Table 4–35 for a complete description of the register contents.
5 TI Extension Registers The TI extension base address register provides a method of accessing memory-mapped TI extension registers. See Section 3.10, TI Extension Base Address Register, for register bit field details. See Table 5–1 for the TI extension register listing. Table 5–1.
5.2 Isochronous Receive Digital Video Enhancements The DV frame synchronous and branch enhancement provides a mechanism in buffer-fill mode to synchronize 1394 DV data that is received in the correct order to DV frame-sized data buffers described by several INPUT_MORE descriptors (see 1394 Open Host Controller Interface Specification, Revision 1.1).
Table 5–2. Isochronous Receive Digital Video Enhancements Register Description (Continued) BIT FIELD NAME TYPE DESCRIPTION 8 CIP_Strip2 RSC When bit 8 is set to 1, the isochronous receive context 2 strips the first two quadlets of payload. This bit is only interpreted when bit 30 (isochHeader) in the isochronous receive context control register at OHCI offset 440h/444h (see Section 4.44, Isochronous Receive Context Control Register) is cleared to 0. 7–6 RSVD R 5 DV_Branch1 RSC Reserved.
5.4 Link Enhancement Register This register is a memory-mapped set/clear register that is an alias of the link enhancement control register at PCI offset F4h. These bits may be initialized by software. Some of the bits may also be initialized by a serial EEPROM, if one is present, as noted in the bit descriptions below. If the bits are to be initialized by software, the bits must be initialized prior to setting bit 19 (LPS) in the host controller control register at OHCI offset 50h/54h (see Section 4.
Table 5–3. Link Enhancement Register Description (Continued) 7 enab_unfair RSC Enable asynchronous priority requests. iOHCI-Lynx compatible. Setting bit 7 to 1 enables the link to respond to requests with priority arbitration. It is recommended that this bit be set to 1.
6 Serial EEPROM Interface The TSB43AB23 device provides a serial bus interface to initialize the GUID registers and a few PCI configuration registers through a serial EEPROM. The TSB43AB23 device communicates with the serial EEPROM via the 2-wire serial interface. After power up the serial interface initializes the locations listed in Table 6–1. While the TSB43AB23 device accesses the serial EEPROM, all incoming PCI slave accesses are terminated with retry status.
Table 6–2. Serial EEPROM Map EEPROM BYTE ADDRESS 00 BYTE DESCRIPTION PCI maximum latency (0h) PCI_minimum grant (0h) 01 PCI vendor ID 02 PCI vendor ID (msbyte) 03 PCI subsystem ID (lsbyte) 04 PCI subsystem ID (msbyte) 05 06 [7] Link_enhancement Control.enab_unfair [6] HCControl.
7 PHY Register Configuration There are 16 accessible internal registers in the TSB43AB23 device. The configuration of the registers at addresses 0h through 7h (the base registers) is fixed, whereas the configuration of the registers at addresses 8h through Fh (the paged registers) is dependent upon which one of eight pages, numbered 0h through 7h, is currently selected. The selected page is set in base register 7h. 7.
Table 7–2. Base Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Physical ID 6 R This field contains the physical address ID of this node determined during self-ID. The physical ID is invalid after a bus reset until self-ID has completed as indicated by an unsolicited register-0 status transfer. R 1 R Root. This bit indicates that this node is the root node. The R bit is cleared to 0 by bus reset and is set to 1 during tree-ID if this node becomes root. CPS 1 R Cable-power-status.
Table 7–2. Base Register Field Descriptions (Continued) FIELD ISBR SIZE TYPE DESCRIPTION 1 R/W Initiate short arbitrated bus reset. This bit, if set to 1, instructs the PHY layer to initiate a short (1.3 µs) arbitrated bus reset at the next opportunity. This bit is cleared to 0 by a bus reset. NOTE: Legacy IEEE Std 1394-1995 compliant PHY layers can not be capable of performing short bus resets.
7.2 Port Status Register The port status page provides access to configuration and status information for each of the ports. The port is selected by writing 0 to the Page_Select field and the desired port number to the Port_Select field in base register 7. Table 7–3 shows the configuration of the port status page registers and Table 7–4 shows the corresponding field descriptions. If the selected port is not implemented, all registers in the port status page are read as 0. Table 7–3.
Table 7–4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Int_enable 1 R/W Port event interrupt enable. When the Int_enable bit is set to 1, a port event on the selected port sets the port event interrupt (Port_event) bit and notifies the link. This bit is cleared to 0 by a system (hardware) reset and is unaffected by bus reset. Fault 1 R/W Fault.
7.4 Vendor-Dependent Register The vendor-dependent page provides access to the special control features of the TSB43AB23 device, as well as to configuration and status information used in manufacturing test and debug. This page is selected by writing 7 to the Page_Select field in base register 7. Table 7–7 shows the configuration of the vendor-dependent page, and Table 7–8 shows the corresponding field descriptions. Table 7–7.
7.5 Power-Class Programming The PC0–PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21–23) of the transmitted self-ID packet. Table 7–9 shows the descriptions of the various power classes. The default power-class value is loaded following a system (hardware) reset, but is overridden by any value subsequently loaded into the Pwr_Class field in register 4. Table 7–9.
8 Application Information 8.1 PHY Port Cable Connection TSB43AB23 400 kΩ CPS 1 µF Cable Power Pair TPBIAS 56 Ω 56 Ω TPA+ Cable Pair A TPA– Cable Port TPB+ Cable Pair B TPB– 56 Ω 220 pF (see Note A) 56 Ω 5 kΩ Outer Shield Termination NOTE A: IEEE Std 1394-1995 calls for a 250-pF capacitor, which is a nonstandard component value. A 220-pF capacitor is recommended. Figure 8–1.
Outer Cable Shield 0.01 µF 1 MΩ 0.001 µF Chassis Ground Figure 8–2. Typical Compliant DC Isolated Outer Shield Termination Outer Cable Shield Chassis Ground Figure 8–3. Non-DC Isolated Outer Shield Termination 8.2 Crystal Selection The TSB43AB23 device is designed to use an external 24.576-MHz crystal connected between the XI and XO pins to provide the reference for an internal oscillator circuit.
For example, load capacitors (C9 and C10 in Figure 8–4) of 16 pF each were appropriate for the layout of the TSB43AB23 evaluation module (EVM), which uses a crystal specified for 12-pF loading. The load specified for the crystal includes the load capacitors (C9 and C10), the loading of the PHY pins (CPHY), and the loading of the board itself (CBD). The value of CPHY is typically about 1 pF, and CBD is typically 0.8 pF per centimeter of board etch; a typical board can have 3 pF to 6 pF or more.
packet to be transmitted and then a bus reset initiated so as to verify that all nodes on the bus have updated their RHBs and Gap_Count values, without having the Gap_Count set back to 63 by the bus reset. The subsequent connection of a new node to the bus, which initiates a bus reset, then causes the Gap_Count of each node to be set to 63.
9 Electrical Characteristics 9.1 Absolute Maximum Ratings Over Operating Temperature Ranges† Supply voltage range: REG18 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.2 V to 2.2 V AVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.0 V DVDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . – 0.3 V to 4.
9.2 Recommended Operating Conditions TEST CONDITION REG18 Core voltage, AVDD Core voltage, DVDD Core voltage, PLLVDD Output voltage, VO TTL and LVCMOS terminals 3.3 V PCI 5V High-level High level input in ut voltage, VIH† PC(0–2) G_RST Miscellaneous‡ Low-level Low level in input ut voltage, VIL† MAX UNIT 1.6 1.8 2.0 V 3 3.3 3.6 V 3 3.3 3.6 V 2.7 3 3.6 V DVDD V 3 3.3 3.6 4.5 5 5.5 0.475 VDDP 2 VDDP VDDP 0.7 DVDD DVDD 0.6 DVDD DVDD 2 PCI 3.3 V 0 PCI 5V 0 0.
Recommended Operating Conditions (Continued) TEST CONDITION Receive R i input i t skew MIN NOM MAX Between TPA and TPB cable inputs, S100 operation ± 0.8 Between TPA and TPB cable inputs, S200 operation ± 0.55 Between TPA and TPB cable inputs, S400 operation ± 0.5 UNIT ns 9.
9.4 Electrical Characteristics Over Recommended Ranges of Operating Conditions (unless otherwise noted) 9.4.1 Device PARAMETER TEST CONDITIONS MIN See Note 4 Supply S l currentt (internal (i t l voltage lt regulator l t enabled, bl d REG_EN REG EN = L) IDD TYP MAX See Note 5 128 See Note 6 69.8 mA VTH VO Power status threshold, CPS input† Ports disabled VDD = 1.8 V (internal) TA = 25°C Ports disabled VDD = 1.
9.4.3 Receiver PARAMETER TEST CONDITIONS ZID Differential impedance Drivers disabled ZIC Common mode impedance Common-mode Drivers disabled VTH-R VTH-CB Receiver input threshold voltage Drivers disabled Cable bias detect threshold, TPBx cable inputs Drivers disabled VTH+ VTH– Positive arbitration comparator threshold voltage MIN TYP 4 7 MAX UNIT kΩ 4 pF 20 kΩ 24 pF – 30 30 mV 0.6 1.
10 Mechanical Information The TSB43AB23 device is packaged in a 128-terminal PDT package. The following shows the mechanical dimensions for the PDT package. PDT (S-PQFP-G128) PLASTIC QUAD FLATPACK 0,23 0,13 0,40 96 0,05 M 65 97 64 128 33 1 0,13 NOM 32 12,40 TYP Gage Plane 14,05 SQ 13,95 16,10 SQ 15,90 0,05 MIN 0,25 0°–ā5° 0,75 0,45 1,05 0,95 Seating Plane 1,20 MAX 0,08 4087726/A 11/95 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
PGE (S-PQFP-G144) PLASTIC QUAD FLATPACK 108 73 109 72 0,27 0,17 0,08 M 0,50 144 0,13 NOM 37 1 36 Gage Plane 17,50 TYP 20,20 SQ 19,80 22,20 SQ 21,80 0,25 0,05 MIN 0°–ā7° 0,75 0,45 1,45 1,35 Seating Plane 1,60 MAX 0,08 4040147 / C 10/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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