TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 D Fully Supports Provisions of IEEE P1394b D D D D D D D D D D Revision 1.33+ at 1-Gigabit Signaling Rates Fully Supports Provisions of IEEE 1394a−2000 and 1394−1995 Standard for High Performance Serial Bus Fully Interoperable With Firewire™, i.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 description The TSB81BA3D provides the digital and analog transceiver functions needed to implement a three-port node in a cable-based IEEE 1394 network. Each cable port incorporates two differential line transceivers.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 description (continued) Both the twisted pair A (TPA) and the twisted pair B (TPB) cable interfaces incorporate differential comparators to monitor the line states during initialization and arbitration when connected to a 1394a−2000 compliant device. The outputs of these comparators are used by the internal logic to determine the arbitration status.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 description (continued) The LPS (link power status) terminal works with the LKON/DS2 terminal to manage the power usage in the node. The LPS signal from the LLC is used in conjunction with the LCtrl bit (see Table 1 and Table 2 in the APPLICATION INFORMATION section) to indicate the active/power status of the LLC.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 pin assignments TPA0+ TPA0− AVDD−3.3 AGND TPB0+ TPB0− TPBIAS1 TPA1+ TPA1− AVDD−3.3 AGND TPB1+ TPB1− TPBIAS0 TPA2+ TPA2− AVDD−3.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 functional block diagram R0 CPS LPS CNA PINT Bias Voltage and Current Generator Received Data Decoder/Retimer Link Interface I/O TPBIAS1 TPA0+ TPA0− Bilingual Cable Port 0 TPB0+ TPB0− Arbitration and Control State Machine Logic RESETz LKON/DS2 BMODE PD PC0 PC1 PC2 SE SM DS0 DS1 TESTM TESTW Bilingual Cable Port 1 Bilingual Cable Port 2 Crystal Oscillator, PLL System, and Transmit Cloc
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 Terminal Functions TERMINAL I/O DESCRIPTION 21, 40, 43, 50, 61, 62 − Analog circuit ground terminals. These terminals must be tied together to the low-impedance circuit board ground plane. Supply 24, 39, 44, 51, 57, 63 − Analog circuit power terminals. A combination of high-frequency decoupling capacitors near each terminal are suggested, such as paralleled 0.1 μF and 0.001 μF.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION 2 I/O Link-on output/Data-strobe-only input for port 2. This terminal may be connected to the link-on input terminal of the LLC through a 1-kΩ resistor if the link-on input is available on the link layer. Data-strobe-only mode for port 2. 1394a-only port 0 enable programming terminal.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 Terminal Functions (Continued) TERMINAL I/O DESCRIPTION 5 O PHY clock. Provides a 98.304-MHz clock signal, synchronized with data transfers, to the LLC when the PHY-link interface is operating in the 1394b mode (BMODE asserted). PCLK output provides a 49.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 Terminal Functions (Continued) TERMINAL NAME I/O DESCRIPTION 58 59 55 56 I/O Port 2 twisted-pair differential-signal terminals. Board traces from each pair of positive and negative differential signal terminals must be kept matched and as short as possible to the external load resistors and to the cable connector.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 recommended operating conditions Source power node Supply voltage, voltage 3.3 3 3 VDD Nonsource power node Supply voltage, Core VDD LREQ, CTL0, CTL1, D0−D7, LCLK High-level High level input voltage, VIH MIN TYP† MAX 3.0 3.3 3.6 3.0‡ 3.3 3.6 1.85 1.95 2.05 V V 2.6 LKON/DS2, PC0, PC1, PC2, PD, BMODE 0.7×VDD RESETz 0.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) driver PARAMETER † ‡ TEST CONDITION MIN TYP MAX UNIT VOD Differential output voltage 56 Ω, 172 265 mV IDIFF Driver difference current, TPA+, TPA−, TPB+, TPB− Drivers enabled, speed signaling off −1.05† 1.05† mA −2.53‡ mA −8.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 electrical characteristics over recommended ranges of operating conditions (unless otherwise noted) (continued) thermal characteristics PARAMETER TEST CONDITION RθJA Junction-to-free-air thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-free-air thermal resistance RθJC Junction-to-case-thermal resistance RθJA Junction-to-free-air thermal resistance RθJC
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PARAMETER MEASUREMENT INFORMATION xCLK tsu th D, CTL, LREQ Figure 2. Dx, CTLx, LREQ Input Setup and Hold Time Waveforms xCLK td D, CTL Figure 3.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION Table 1.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION Table 2. Base Register Field Descriptions (Continued) SIZE TYPE DESCRIPTION LCtrl FIELD 1 Rd/Wr Link-active status control. This bit controls the indicated active status of the LLC reported in the self-ID packet. The logical AND of this bit and the LPS active status is replicated in the L field (bit 9) of the self-ID packet.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION Table 2. Base Register Field Descriptions (Continued) SIZE TYPE DESCRIPTION EAA FIELD 1 Rd/Wr Enable accelerated arbitration. This bit enables the PHY to perform the various arbitration acceleration enhancements defined in 1394a−2000 (ACK-accelerated arbitration, asynchronous fly-by concatenation, and isochronous fly-by concatenation).
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION Table 4. Page 0 (Port Status) Register Field Descriptions FIELD SIZE TYPE DESCRIPTION Astat 2 Rd TPA line state. This field indicates the instantaneous TPA line state of the selected port, encoded as follows: Code Arb Value 11 Z 01 1 10 0 00 invalid Bstat 2 Rd TPB line state. This field indicates the TPB line state of the selected port.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION Table 4. Page 0 (Port Status) Register Field Descriptions (Continued) FIELD SIZE TYPE DESCRIPTION Max_port_speed 3 Rd/Wr Max_port_speed The maximum speed at which a port is allowed to operate in beta mode.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION The vendor identification page identifies the vendor/manufacturer and compliance level. The page is selected by writing 1 to the Page_Select field in base register 7. Table 5 shows the configuration of the vendor identification page, and Table 6 shows the corresponding field descriptions. Table 5.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION power-class programming The PC0−PC2 terminals are programmed to set the default value of the power-class indicated in the pwr field (bits 21−23) of the transmitted self-ID packet. Descriptions of the various power-classes are given in Table 9.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION power-class programming (continued) Outer Shield Termination TSB81BA3D 400 kΩ CPS VP 1 μF TPBIAS 56 Ω Cable Power Pair 56 Ω 270 pF TPA+ Cable Pair A TPA− TPA_REFGND 0.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION power-class programming (continued) Outer Cable Shield Chassis Ground Figure 6. Non-DC Isolated Outer Shield Termination 10 kΩ Link Power LPS Square Wave Input LPS 10 kΩ Figure 7. Nonisolated Connection Variations for LPS PHY VDD 18 kΩ LPS Square Wave Signal 0.033 μF 13 kΩ PHY GND Figure 8.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION designing with PowerPAD™ The TSB81BA3D is housed in a high performance, thermally enhanced, 80-terminal PFP PowerPAD™ package. Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION using the TSB81BA3D with a non-1394b link layer The TSB81BA3D implements the PHY-LLC interface specified in the 1394b Supplement. This interface is based upon the interface described in Section 14 of IEEE P1394b (draft 1.33). When using a LLC compliant with this interface, the BMODE input must be tied high.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION power-up reset To ensure proper operation of the TSB81BA3D the RESETz terminal must be asserted low for a minimum of 2 ms from the time that PHY power reaches the minimum required supply voltage and the input clock is valid.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 APPLICATION INFORMATION bus reset It is recommended, that whenever the user has a choice, the user should initiate a bus reset by writing to the initiate short bus reset (ISBR) bit (bit 1 PHY register 0101b). Care must be taken to not change the value of any of the other writeable bits in this register when the ISBR bit is written to.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) The TSB81BA3D is designed to operate with an LLC such as the Texas Instruments TSB12LV21B, TSB12LV26, TSB12LV32, TSB42AA4, or TSB12LV01B when the BMODE terminal is tied low. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive. The LLC issues a service request to read or write a PHY register, to request the PHY to gain control of the serial-bus in order to transmit a packet, or to control arbitration acceleration.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) LLC service request (continued) The length of the stream varies depending on the type of request as shown in Table 12. Table 12.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) LLC service request (continued) NOTE: The TSB81BA3D accepts a bus request with an invalid speed code and processes the bus request normally. However, during packet transmission for such a request, the TSB81BA3D ignores any data presented by the LLC and transmits a null packet.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) LLC service request (continued) To send an acknowledge packet, the LLC must issue an immediate bus request (ImmReq) during the reception of the packet addressed to it. This is required in order to minimize the idle gap between the end of the received packet and the start of the transmitted acknowledge packet.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. The PHY waits until the interface is idle before starting the transfer.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) status transfer (continued) The sequence of events for a status transfer is as follows: (a) Status transfer initiated. The PHY indicates a status transfer by asserting status on the CTL lines along with the status data on the D0 and D1 lines (only 2 bits of status are transferred per cycle).
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) receive (continued) The sequence of events for a normal packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) transmit When the LLC issues a bus request through the LREQ terminal, the PHY arbitrates to gain control of the bus. If the PHY wins arbitration for the serial bus, then the PHY-LLC interface bus is granted to the LLC by asserting the grant state (11b) on the CTL terminals for one PCLK cycle, followed by idle for one clock cycle.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) transmit (continued) The sequence of events for a normal packet transmission is as follows: (a) Transmit operation initiated. The PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link so that the link may transmit a packet.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) transmit (continued) The sequence of events for a cancelled/null packet transmission is as follows: (a) Transmit operation initiated. PHY asserts grant on the CTL lines followed by idle to hand over control of the interface to the link. (b) Optional idle cycle. The link may assert at most one idle cycle preceding assertion of hold.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) interface reset and disable (continued) The LLC requests that the interface be reset by deasserting the LPS signal and terminating all bus and request activity. When the PHY observes that LPS has been deasserted for TLPS_RESET, it resets the interface.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) interface reset and disable (continued) (a) (c) (d) PCLK CTL0, CTL1 D0 − D7 (b) LREQ LPS TLPS_RESET TLPS_DISABLE Figure 18. Interface Disable The sequence of events for disabling the PHY-LLC is as follows: (a) Normal operation.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394a−2000 INTERFACE) interface reset and disable (continued) ISO (high) 7 Cycles SYSCLK (b) (c) CTL0 (d) CTL1 D0 − D7 LREQ (a) LPS TCLK_ACTIVATE Figure 19. Interface Initialization The sequence of events for initialization of the PHY-LLC is as follows: (a) LPS reasserted.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) The TSB81BA3D is designed to operate with a LLC such as the Texas Instruments TSB82AA2 when the BMODE terminal is tied high. Details of operation for the Texas Instruments LLC devices are found in the respective LLC data sheets. The following paragraphs describe the operation of the PHY-LLC interface.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) The TSB81BA3D normally controls the CTL0−CTL1 and D0−D7 bidirectional buses. The LLC is allowed to drive these buses only after the LLC has been granted permission to do so by the PHY. There are four operations that may occur on the PHY-LLC interface: link service request, status transfer, data transmit, and data receive.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 24.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 26. Bus Request BIT(s) 0 NAME DESCRIPTION Start bit Indicates the beginning of the transfer (always 1) Request type Indicates the type of bus request. See Table 25. 5 Request format Indicates the packet format to be used for packet transmission. See Table 27.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) LLC service request (continued) Table 30.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) status transfer A status transfer is initiated by the PHY when there is status information to be transferred to the LLC. Two types of status transfers may occur: bus status transfer and PHY status transfer.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) status transfer (continued) PHY status transfers use the PINT terminal to serially send status information to the LLC as shown in Figure 23. PHY status transfers (Table 33) can occur at any time during normal operation.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) receive When the PHY detects the data-prefix state on the serial bus, it initiates a receive operation by asserting receive on the CTL terminals and a logic 1 on each of the D terminals (data-on indication). The PHY indicates the start of a packet by placing the speed code (encoded as shown in Table 35) on the D terminals, followed by packet data.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) receive (continued) PCLK CTL0, CTL1 10 01 (a) D0–D7 XX 10 00 (e) (b) STATUS FF (data-on) FF (data-on) (c) (d) SPD d0 dn 00 NOTE A: SPD = Speed code, see Table 35. d0–dn = Packet data. STATUS = status bits, see Table 32. Figure 25.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) receive (continued) The sequence of events for a null packet reception is as follows: (a) Receive operation initiated. The PHY indicates a receive operation by asserting receive on the CTL lines. Normally, the interface is idle when receive is asserted.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) PHY CTL[0:1] 00 11 00 ZZ ZZ ZZ ZZ ZZ ZZ PHY D[0:7] 00 GT 00 ZZ ZZ ZZ ZZ ZZ ZZ LLC CTL[0:1] ZZ ZZ ZZ ZZ ZZ 11 11 01 01 LLC D[0:7] ZZ ZZ ZZ ZZ ZZ 00 00 d0 d1 PHY CTL[0:1] ZZ ZZ ZZ ZZ ZZ ZZ 00 00 00 PHY D[0:7] ZZ ZZ ZZ ZZ ZZ ZZ 00 00 00 LLC CTL[0:1] LLC D[0:7] GT = Grant Ty
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) Table 36. Link Request Type Encoding During Packet Transmission D1−D3 Request Type 000 No request 001 Isoch_Req_Odd 010 Isoch_Req_Even 011 Current 100 Next_Even 101 Next_Odd 110 Cyc_Start_Req 111 Reserved Table 37.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 PRINCIPLES OF OPERATION (1394B INTERFACE) transmit (continued) Table 41. Grant Type Values During Grant Cycle [D1−D3] VALUE DURING GRANT CYCLE REQUEST TYPE 000 Reserved 001 Reserved 010 Isochronous grant 011 Reserved 100 Reserved 101 Asynchronous grant 110 Cycle start grant 111 Immediate grant Table 42.
TSB81BA3D, TSB81BA3DI IEEE 1394b THREE-PORT CABLE TRANSCEIVER/ARBITER SLLS559E − DECEMBER 2002 − REVISED JUNE 2006 THERMAL PAD MECHANICAL DATA This PowerPAD™ package incorporates an exposed thermal pad that is designed to be attached directly to an external heatsink. When the thermal pad is soldered directly to the printed circuit board (PCB), the PCB can be used as a heatsink.
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