TSC2003 TSC 2003 TSC2 003 SBAS162G – NOVEMBER 2000 – REVISED JUNE 2007 I2C TOUCH SCREEN CONTROLLER DESCRIPTION FEATURES ● 2.5V TO 5.25V OPERATION ● INTERNAL 2.5V REFERENCE ● DIRECT BATTERY MEASUREMENT (0.5V TO 6V) ● ON-CHIP TEMPERATURE MEASUREMENT ● TOUCH-PRESSURE MEASUREMENT ● I2C INTERFACE SUPPORTS: Standard, Fast, and High-Speed Modes ● AUTO POWER DOWN ● TSSOP-16 AND VFBGA-48 PACKAGES The TSC2003 is a 4-wire resistive touch screen controller.
PACKAGE/ORDERING INFORMATION(1) MAXIMUM RELATIVE ACCURACY (LSB) MAXIMUM GAIN ERROR (LSB) PACKAGE-LEAD PACKAGE DESIGNATOR TSC2003 TSC2003 TSC2003 TSC2003 ±2 ±2 ±2 ±2 ±4 ±4 ±4 ±4 TSSOP-16 TSSOP-16 TSSOP-16 TSSOP-16 TSC2003 TSC2003 ±2 ±2 ±4 ±4 VFBGA-48 VFBGA-48 PRODUCT SPECIFIED TEMPERATURE RANGE PACKAGE MARKING ORDERING NUMBER PW PW PW PW –40°C –40°C –40°C –40°C TSC2003I TSC2003I TSC2003I TSC2003I TSC2003IPW TSC2003IPWT TSC2003IPWR TSC2003IPWRG4 ZQC ZQC –40°C to +85°C –40°C to +85°C BC20
ELECTRICAL CHARACTERISTICS At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless otherwise noted.
ELECTRICAL CHARACTERISTICS (Cont.) At TA = –40°C to +85°C, +VDD = +2.7V, VREF = 2.5V external voltage, I2C bus frequency = 3.4MHz, 12-bit mode and digital inputs = GND or +VDD, unless otherwise noted. TSC2003I PARAMETER CONDITIONS POWER-SUPPLY REQUIREMENTS +VDD MIN Specified Performance Operating Range Internal Reference OFF, PD1 = PD0 = 0 High-Speed Mode: SCL = 3.
TIMING CHARACTERISTICS At TA = –40°C to +85°C, +VDD = +2.7V, unless otherwise noted. All values referred to VIHMIN and VILMAX levels. PARAMETER SYMBOL CONDITIONS MIN MAX UNITS SCL Clock Frequency fSCL Standard Mode Fast Mode High-Speed Mode, Cb = 100pF max High-Speed Mode, Cb = 400pF max 0 0 0 0 100 400 3.4 1.7 kHz kHz MHz MHz Bus Free Time Between a STOP and Start Condition tBUF Standard Mode Fast Mode 4.7 1.3 µs µs Standard Mode Fast Mode High-Speed Mode 4.
POWER-ON SEQUENCE TIMING During TSC2003 power-up, the I2C bus should be idle. In other words, the SDA and SCL lines must be high before the TSC supply (+VDD) ramps up greater than 0.9V. If the TSC uses the same supply as the the I2C bus pull-up resistors (VI2C), then a 1µF capacitor placed very close to the TSC supply pin will cause the TSC supply to ramp up more slowly (refer to the Power-On Sequence timing diagram).
TYPICAL CHARACTERISTICS: +2.7V At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted. SUPPLY CURRENT vs VDD SUPPLY CURRENT vs TEMPERATURE 300 High-Speed Mode = 3.4MHz Supply Current (µA) Supply Current (µA) 250 200 150 Fast Mode = 400kHz 100 50 Standard Mode = 100kHz 0 –40 –20 0 20 40 60 80 1200 1100 1000 900 800 700 600 500 400 300 200 100 0 High-Speed Mode = 3.4MHz Fast Mode = 400kHz Standard Mode = 100kHz 2.5 100 3.0 3.5 4.
TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted. EXTERNAL REFERENCE CURRENT vs TEMPERATURE 6.0 10 5.0 9 External Reference Current (µA) Offset Delta from +25°C (LSB) CHANGE IN OFFSET vs TEMPERATURE 4.0 3.0 2.0 1.0 0.0 –1.0 –2.0 –3.0 –4.0 –5.0 8 High-Speed Mode = 3.4MHz 7 6 5 4 Fast Mode = 400kHz 3 Standard Mode = 100kHz 2 1 0 –6.
TYPICAL CHARACTERISTICS: +2.7V (Cont.) At TA = +25°C, +VDD = +2.7V, VREF = External +2.5V, I2C bus frequency = 3.4MHz, PD1 = PD0 =0, unless otherwise noted. TEMP DIODE VOLTAGE vs TEMPERATURE TEMP0 DIODE VOLTAGE vs VDD (25°C) 850 614 TEMP1 TEMP0 Diode Voltage (mV) Temp Diode Voltage (mV) 800 750 700 650 600 TEMP0 550 500 450 613 612 611 –40 –35 –30 –25 –20 –15 –10 –05 0 05 10 15 20 25 30 35 40 45 50 55 60 65 70 75 80 85 610 2.5 3.0 3.5 Temperature (°C) 4.0 4.5 5.0 5.
THEORY OF OPERATION a differential input to the converter, and a differential reference architecture, it is possible to negate the switch’s onresistance error (should this be a source of error for the particular measurement). The TSC2003 is a classic Successive Approximation Register (SAR) Analog-to-Digital (A/D) converter. The architecture is based on capacitive redistribution which inherently includes a sample-and-hold function. The converter is fabricated on a 0.6µ CMOS process.
+VDD PENIRQ TEMP1 VREF TEMP0 C2-C0 (Shown 101B) C3 (Shown HIGH) X+ X– Ref ON/OFF Y+ +IN Y– +REF Converter –IN 2.5V Reference –REF 7.5kΩ VBAT1 7.5kΩ VBAT2 2.5kΩ 2.5kΩ Battery On Battery On IN1 IN2 GND FIGURE 2. Simplified Diagram of the Analog Input. INTERNAL REFERENCE Reference Power Down The TSC2003 has an internal 2.5V voltage reference that can be turned ON or OFF with the power-down control bits, PD0 and PD1 (see Table II and Figure 3).
REFERENCE INPUT REFERENCE MODE The voltage difference between +REF and –REF (see Figure 2) sets the analog input range. The TSC2003 will operate with a reference in the range of 2V to +VDD. There are several critical items concerning the reference input and its wide-voltage range. As the reference voltage is reduced, the analog voltage weight of each digital output code is also reduced.
Differential reference mode always uses the supply voltage, through the drivers, as the reference voltage for the A/D converter. VREF cannot be used as the reference voltage in differential mode. It is possible to use a high-precision reference on VREF in single-ended reference mode for measurements which do not need to be ratiometric (i.e., battery voltage, temperature measurement, etc.). In some cases, it could be possible to power the converter directly from a precision reference.
BATTERY MEASUREMENT An added feature of the TSC2003 is the ability to monitor the battery voltage on the other side of the voltage regulator (DC/DC converter), as shown in Figure 7. The battery voltage can vary from 0.5V to 6V, while the voltage regulator maintains the voltage to the TSC2003 at 2.7V, 3.3V, etc. The input voltage (VBAT1 or VBAT2) is divided down by 4 so that a 6.0V battery voltage is represented as 1.5V to the A/D converter. The simplifies the multiplexer and control logic.
serial clock (SCL), controls the bus access, and generates the START and STOP conditions. The TSC2003 operates as a slave on the I2C bus. Connections to the bus are made via the open-drain I/O lines SDA and SDL. stable LOW during the HIGH period of the acknowledge clock pulse. Of course, setup and hold times must be taken into account. A master must signal an end of data to the slave by not generating an acknowledge bit on the last byte that has been clocked out of the slave.
Address Byte The address byte, as shown in Figure 10, is the first byte received following the START condition from the master device. The first five bits (MSBs) of the slave address are factory preset to 10010. The next two bits of the address byte are the device select bits: A1 and A0. Input pins (A1-A0) on the TSC2003 determine these two bits of the device address for a particular TSC2003. Therefore, a maximum of four devices with the same preset code can be connected on the same bus at one time.
Read A Conversion/Read Cycle Once the master receives the acknowledge bit from the TSC2003, the master writes the command byte to the slave (see Figure 11). After the command byte is received by the slave, the slave issues another acknowledge bit. The master then ends the Write Cycle by issuing a repeated START or a STOP condition, as shown in Figure 12.
I2C High-Speed Operation FS = Full-Scale Voltage = VREF(1) 1LSB = VREF(1)/4096 The TSC2003 can operate with high-speed I2C masters. To do so, the simple resistor pull-up on SCL must be changed to the active pull-up, as recommended in the I2C specification. 1LSB 11...111 I2C bus will be operating in standard or fast mode The initially. Following a START condition, the master will send the code 00001xxx, which the slave will not acknowledge. At this point, the bus is now operating in high-speed mode.
For optimum performance, care should be taken with the physical layout of the TSC2003 circuitry. The basic SAR architecture is sensitive to glitches or sudden changes on the power supply, reference, ground connections, and digital inputs that occur just prior to latching the output of the analog comparator. Therefore, during any single conversion for an n-bit SAR converter, there are n “windows” in which large external transient voltages can easily affect the conversion result.
Revision History DATE REVISION PAGE SECTION 6/07 G 6 Timing DESCRIPTION Added Power-On Sequence Timing section. NOTE: Page numbers for previous revisions may differ from page numbers in the current version. TSC2003 20 www.ti.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TSC2003IPWR TSSOP PW 16 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1 TSC2003IZQCR BGA MI CROSTA R JUNI OR ZQC 48 2500 330.0 12.4 4.3 4.3 1.5 8.0 12.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSC2003IPWR TSSOP PW 16 2500 367.0 367.0 35.0 TSC2003IZQCR BGA MICROSTAR JUNIOR ZQC 48 2500 338.1 338.1 20.
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