TSC2301 SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 PROGRAMMABLE TOUCH SCREEN CONTROLLER WITH STEREO AUDIO CODEC FEATURES APPLICATIONS • • • • • • • • • • • • • • • • SPI™ Serial Interface Touch Screen Controller – 4-Wire Touch Screen Interface – Internal Detection of Screen Touch and Keypad Press – Touch Pressure Measurement – Ratiometric Conversion – Programmable 8-, 10- or 12-Bit Resolution – Programmable Sampling Rates Up to 125 kHz – Direct Battery Measu
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 MICBIAS AFILTR AFILTL I2SDIN AVDD - 1V AVDD 30k Ω I2S INTERFACE VCM I2SDOUT LRCLK 20k Ω BCLK AGND Mute, 0db, 6dB, 12dB MICIN +20 to - 40dB, 0.5dB Steps 317Ω Σ∆ ADC RLINEIN +12dB to 35dB 0.5dB steps +20 to - 40dB, 0.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS At 25°C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted. Parameter Conditions TSC2301 Min Typ Units Max Auxilary Analog Inputs Input voltage range 0 Input capacitance Input leakage current +VREFIN V 25 ρF 1 µA Battery Monitor Input Input voltage range 0 6.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 ELECTRICAL CHARACTERISTICS (continued) At 25°C, HPVDD = AVDD = DVDD = +3.3 V, VREF = External 2.5 V, unless otherwise noted. Parameter Conditions Output power per channel TSC2301 Min Typ R = 32 Ω 14 mW R = 16 Ω 27 mW R = 16 Ω VDD = 3.6V 32 mW 96 dB Signal-to-noise ratio, A-weighted 85 Total harmonic distortion Units Max R = 32 Ω 1-kHz, 0-dB input -83 R = 16 Ω 1-kHz, -3-dB input -77 dB 1.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 PIN DESCRIPTION (continued) VFBGA BALL TQFP PIN I/O NAME B2 16 I SS DESCRIPTION Slave select input (active low). Data is not clocked into MOSI unless SS is low. When SS is high, MISO is high impedance. B1 17 I SCLK SPI clock input C2 18 I MOSI SPI data input. Data is clocked in at SCLK rising edge C1 19 O MISO SPI data output. Data is clocked out at SCLK falling edge. High impedance when SS is high.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 PIN DESCRIPTION (continued) VFBGA BALL TQFP PIN I/O NAME DESCRIPTION D10 61 I Y+ C11 62 I HPVDD B11 63 I AUX1 SAR auxiliary analog input 1 B10 64 I AUX2 SAR auxiliary analog input 2 Y+ position input Analog supply for headphone amplifier and touch screen circuitry TIMING DIAGRAM SS tLag t sck tLead twsck SCLK tf t td tr twsck tv tho MSB OUT MISO tdis BIT . . .
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. CHANGE IN GAIN ERROR vs TEMPERATURE CHANGE IN OFFSET ERROR vs TEMPERATURE 1 0.5 2 0.4 1.95 0.3 0 –0.5 –1 –1.5 1.9 0.2 1.85 0.1 Idd (mA) Change in Error (LSB) Change in Error (LSB) 0.5 CONVERSION SUPPLY CURRENT vs TEMPERATURE 0 –0.1 1.7 –0.3 1.65 –0.5 –50 0 50 1.75 –0.2 –0.4 –2 –50 1.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. INTERNAL 2.5-V REFERENCE vs TEMPERATURE DAC OUTPUT CURRENT vs TEMPERATURE 1.27 1.15 1.26 2.485 1.255 2.48 1.25 1.245 2.475 1.24 2.47 1.235 2.465 DAC Output Current (mA) 1.265 2.49 0 50 1.1 1.05 1 700 600 0.95 1.23 2.46 –50 800 Temp2 Voltage (mV) 2.495 Vref (V) 900 1.2 1.275 2.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. SNR OF DAC (LINEOUT) vs TEMPERATURE THD OF ADC (LINEIN) vs TEMPERATURE 99 –62.000 98.875 –63.000 SNR OF ADC (LINEIN) vs TEMPERATURE 90 89 –64.000 98.75 88 –65.000 98.5 –66.000 SNR (dB) THD (dB) SNR (dB) 98.625 –67.000 –68.000 98.375 –69.000 98.25 87 86 85 –70.000 98.125 84 –71.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. TEMP2 DIODE VOLTAGE vs SUPPLY VOLTAGE TEMP1 DIODE VOLTAGE vs SUPPLY VOLTAGE 730 INTERNAL OSCILLATOR FREQUENCY vs SUPPLY VOLTAGE 9 611 610.6 Temp1 Voltage (mV) Temp2 Voltage (mV) Internal Oscillator Frequency (MHz) 610.8 728 726 724 610.4 610.2 610 609.8 609.6 609.4 722 609.2 609 720 2.5 3 8.7 8.6 3.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. INL MINIMUM vs SUPPLY VOLTAGE CONVERSION SUPPLY CURRENT vs SUPPLY VOLTAGE MICBIAS vs SUPPLY VOLTAGE 2 –1.5 2.5 2.4 –1.75 2.3 –2.25 –2.5 2.2 Vmicbias (V) –2 Idd_Total (mA) INL_Min (LSB) 1.75 1.5 2.1 2 1.9 1.8 1.7 1.25 1.6 –2.75 1.5 1 –3 2.5 2.5 2.5 3 3 3.5 3.5 3 Vdd (V) 3.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. THD OF DAC (HP DRIVER) vs SUPPLY VOLTAGE SNR OF DAC (HP DRIVER) vs SUPPLY VOLTAGE –78 99 89 –79 98 88 –80 97 87 –81 86 SNR (dB) 90 THD (dB) SNR (dB) SNR OF ADC (LINEIN) vs SUPPLY VOLTAGE –82 96 95 85 –83 94 84 –84 93 83 2.5 3 –85 2.5 3.5 92 3 2.5 3.5 3 3.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TYPICAL CHARACTERISTICS (continued) At TA = +25°C, +VDD = +3.3 V, VREF = +2.5 V, fSAMPLE = 125 kHz, unless otherwise noted. SNR OF MONO PATH vs SUPPLY VOLTAGE 102 101 SNR (dB) 100 99 98 97 96 2.5 3 3.5 Vdd (V) Figure 43. OVERVIEW The TSC2301 is an analog interface circuit for human interface devices. A register-based architecture eases integration with microprocessor-based systems through a standard SPI bus.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 OVERVIEW (continued) MICROPHONE JACK Line Inputs Rbias A A HEADPHONE JACK KEYPAD 1 µF 15 14 13 12 A 1nF A 1 to 10 µF A 0.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 DETAILED DESCRIPTION (continued) The TSC2301 supports the resistive 4-wire configuration (see Figure 44). The circuit determines location in two coordinate pair dimensions, although a third dimension can be added for measuring pressure. The 4-Wire Touch Screen Coordinate Pair Measurement A 4-wire touch screen is constructed as shown in Figure 45. It consists of two transparent resistive layers separated by insulating spacers.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 R TOUCH R X–position X–plate 4096 4096 1 Z 1 R 1 Y–position 4096 Y–plate (2) Measure X-Position X+ Y+ Touch X-Position X– Y– Measure Z1-Position Y+ X+ Touch Z-Position X– X+ Y– Y+ Touch Z 2 –Position X– Y– Measure Z2-Position Figure 46.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 The ADC is controlled by an ADC control register. Several modes of operation are possible, depending upon the bits set in the control register. Channel selection, scan operation, averaging, resolution, and conversion rate may all be programmed through this register. These modes are outlined in the sections below for each type of analog input. The results of conversions made are stored in the appropriate result register.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Reference The TSC2301 has an internal voltage reference that can be set to 1.2 V or 2.5 V, through the reference control register. This reference can also be set to automatically power down between conversions to save power, or remain on to reduce settling time. The internal reference voltage is only used in the single-ended mode for battery monitoring, temperature measurement, and for utilizing the auxiliary inputs.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 PENIRQ VDD VDD TEMP1 TEMP2 Internal 50 k Y+ High Except When TEMP1, TEMP2 Activated TEMP DIODE X+ Y– ON Y+ or X+ Drivers on, or TEMP1, TEMP2 Measurements Activated Figure 49.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 DIGITAL INTERFACE The TSC2301 communicates through a standard SPI bus. The SPI allows full-duplex, synchronous, serial communication between a host processor (the master) and peripheral devices (slaves). The SPI master generates the synchronizing clock and initiates transmissions. The SPI slave devices depend on a master to start and synchronize transmissions. A transmission begins when initiated by an SPI master.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Continuous writing is generally not recommended for the control registers, but for the coefficients of bass-boost filter coefficient registers, continuous writing works. Writing to these registers consists of the processor writing the command 0x10E0, which specifies a write operation, with PG1 set to 1, and the ADDR bits set to 07h.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TSC2301 MEMORY MAP The TSC2301 has several 16-bit registers that allow control of the device as well as providing a location for results from the TSC2301 to be stored until read by the host microprocessor. These registers are separated into three pages of memory in the TSC2301: a data page (Page 0), a control page (Page 1), and an audio control page (Page 2). The memory map is shown in Table 3. Table 3.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TSC2301 REGISTER OVERVIEW Table 4.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 4.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 4.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TSC2301 TOUCH SCREEN CONTROL REGISTERS This section describes each of the registers shown in the memory map of Figure 54. The registers are grouped according to the function they control. In the TSC2301, bits in control registers can refer to slightly different functions depending upon whether you are reading the register or writing to it. A summary of all registers and bit locations is shown in Table 4.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [13:10] — AD3 - AD0 ADC Function Select bits. These bits control which input is to be converted, and what mode the converter is placed in. These bits are the same whether reading or writing. See Table 7 for a complete listing of how these bits are used. Table 7. ADC Function Select A/D3 A/D2 A/D1 A/D0 Function 0 0 0 0 Invalid. No registers are updated. This is the default state after a reset.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits[7:6] — AV1, AV0 Converter Averaging Control. These two bits (see Table 9) allow you to specify the number of averages the converter performs. Note that when averaging is used, the STS/STP bit and the DAV output indicates that the converter is busy until all conversions necessary for the averaging are complete. The default state for these bits is 00, selecting no averaging. These bits are the same whether reading or writing. Table 9.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB DPD X X X X X X X X X X X X X X X Bit 15 — DPD DAC Power Down. This bit controls whether the DAC is powered up and operational, or powered down. If the DAC is powered down, the AOUT pin neither sinks nor sources current. Table 12.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 15. PDN Bit Operation PDN Value Description 0 Internal reference is powered at all times 1 Internal reference is powered down between conversions. (default) Note that the PDN bit, in concert with the INT bit, creates a few possibilities for reference behavior. These are detailed in Table 16. Table 16. Reference Behavior Possibilities INT PDN 0 0 Reference Behavior External reference used, internal reference powered down.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [5:3] — PRE[2:0] Precharge time selection bits. These bits set the amount of time allowed for precharging any pin capacitance on the touch screen prior to sensing if the screen is being touched. Table 18. Precharge Times PRE[2:0] PRE2 PRE1 PRE0 0 0 0 Time 20 µs (default) 0 0 1 84 µs 0 1 0 276 µs 0 1 1 340 µs 1 0 0 1.044 ms 1 0 1 1.108 ms 1 1 0 1.300 ms 1 1 1 1.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 TSC2301 KEYPAD REGISTERS The keypad scanner hardware in the TSC2301 is controlled by two registers: the keypad control register and the keypad mask register. The keypad control register controls general keypad functions such as scanning and de-bouncing, while the keypad mask register allows you to mask certain keys from being detected at all.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Keypad Mask Register (Page 1, Address 10H) The Keypad Mask register is formatted as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB M15 M14 M13 M12 M11 M10 M9 M8 M7 M6 M5 M4 M3 M2 M1 M0 This is the same format as used in the keypad data register (Page 0, Address 04H). Each bit in these registers represents one key on the keypad.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 15 — SDAV (write only) SPI Data Available. This read-only bit mirrors the function of the DAV pin. This bit is provided so that the host processor can poll the SPI interface to see whether data is available, without dedicating a GPIO pin from the host processor to the TSC2301 DAV pin. This bit is normally high, goes low when touch screen or keypad data is available, and is reset high when all the new data has been read.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 12 — PCTE PLL Control Enable. This bit allows the user to manually control the audio codec internal PLL. This allows the user to modify the contents of bits [11-0] to control the audio codec PLL. Writing a 0 to this bit enables manual control of the PLL. Otherwise, the PLL is set automatically based on the settings of MCLK [1:0] and I2SFS[3:0] in the audio control register (bits 7-2 in register 00h, page 2). Table 27.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 28. PLL Settings (continued) MCLK (MHz) Desired Fout(MHz) 19.68 22.5792 P A N Actual Fout(MHz) % Error 9 3 7 22.59556 0.072 TSC2301 DATA REGISTERS The data registers of the TSC2301 hold data results from conversions or keypad scans, or the value of the DAC output current. All of these registers default to 0000H upon reset, except the DAC register, which is set to 0080H, representing the midscale output of the DAC.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 If only X and Y coordinates are to be measured, then the conversion process is complete. Figure 51 shows a flowchart for this process. The time it takes to go through this process depends upon the selected resolution, internal conversion clock rate, averaging selected, panel voltage stabilization time, and precharge and sense times.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Conversion Controlled by TSC2301 Initiated By Host Responding to PENIRQ This mode is provided for users who want more control over the A/D conversion process. This mode requires more overhead from the host processor, so it is generally not recommended. In this mode, the TSC2301 detects when the touch panel is touched and causes the PENIRQ line to go low.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 host recognizes the interrupt request. Instead of starting a sequence in the TSC2301, which then reads each coordinate in turn, the host now must control all aspects of the conversion. An example sequence would be: (a) PENIRQ goes low when screen is touched. (b) Host writes to TSC2301 to turn on X-drivers. (c) Host waits a desired delay for panel voltage stabilization. (d) Host writes to TSC2301 to begin X-conversion.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 OPERATION - TEMPERATURE MEASUREMENT In some applications, such as estimating remaining battery life or setting RAM refresh rate, a measurement of ambient temperature is required. The temperature measurement technique used in the TSC2301 relies on the characteristics of a semiconductor junction operating at a fixed current level. The forward diode voltage (VBE) has a well-defined characteristic versus temperature.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Temperature Input 1 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Programmed Delay) Power Down ADC Power up ADC Power Down Reference Convert Temperature Input 1 Set /DAV = 0 N Is Data Averaging Done Turn off clock Y DONE Store Temperature Input 1 in TEMP1 Register Figure 62.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Temperature Input 2 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power Down ADC Power up ADC Power Down Reference Convert Temperature Input 2 Set /DAV = 0 N Is Data Averaging Done Turn off clock Y Store Temperature Input 2 in TEMP2 Register DONE Figure 63.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 2.7 V DC/DC Converter Battery 0.5 V+ to 6.0 V + VCC 0.125 V to 1.5 V VBAT1 ADC 7.5 k 2.5 k 2.7 V DC/DC Converter Battery 0.25 V+ to 3.0 V + VCC 0.125 V to 1.5 V VBAT2 ADC 5.0 k 5.0 k Figure 64. VBAT Example Battery Measurement Functional Block Diagrams, VDD = 2.7 V, VREF = 2.5 V Flowcharts which detail the process of making a battery input reading are shown in Figure 65 and Figure 66.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Battery Input 1 Host Writes A/D Converter Control Register Start Clock Power Down ADC Power Up Reference (Including Delay) Power Down Reference Power up ADC N Convert Battery Input 1 Set /DAV = 0 Is Data Averagin Done Turn off clock Y DONE Store Battery Input 1 in BAT1 Register Figure 65. VBAT1 Measurement Process This assumes the reference control register is configured to power up the internal reference when needed.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Battery Input 2 Host Writes A/D Converter Control Register Start Clock Power Down ADC Power Up Reference (Including Delay) Power Down Reference Power up ADC N Convert Battery Input 2 Set /DAV = 0 Is Data Averaging Done Turn off clock Y DONE Store Battery Input 2 in BAT2 Register Figure 66.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Auxiliary Input 1 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power Down ADC Power up ADC Power Down Reference Convert Auxiliary Input 1 Set /DAV = 0 N Is Data Averaging Done Turn off clock Y DONE Store Auxiliary Input 1 in AUX1 Register Figure 67.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Auxiliary Input 2 Host Writes A/D Converter Control Register Start Clock Power Up Reference (Including Delay) Power Down ADC Power up ADC Power Down Reference Convert Auxiliary Input 2 Set /DAV = 0 N Is Data Averaging Done Turn off clock Y DONE Store Auxiliary Input 2 in AUX2 Register Figure 68.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 OPERATION - PORT SCAN If measurements of all the battery and auxiliary inputs are required, the port scan mode can be used. This mode causes the TSC2301 to sample and convert both battery inputs and both auxiliary inputs. At the end of this cycle, the battery and auxiliary data registers contain the updated values, and the DAV pin is asserted low, signaling the host to read the data.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 OPERATION - D/A CONVERTER The TSC2301 has an onboard 8-bit DAC, configured as shown in Figure 70. This configuration yields a current sink (AOUT) controlled by the value of a resistor connected between the ARNG pin and ground. The D/A converter has a control register, which controls whether or not the converter is powered up. The eight-bit data is written to the DAC through the DAC data register.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 DAC FULLSCALE OUTPUT CURRENT vs RRNG RESISTOR VALUE 1100 DAC Fullscale Output Current – µ A 1000 900 800 700 600 500 400 300 200 100 0 10 k 100 k 1M 10 M 100 M RRNG Resistor Value Figure 71. DAC Output Current Range vs RRNG Resistor Value For example, consider an LCD that has a contrast control voltage VBIAS that can range from 2 V to 4 V, that draws 400 µA when used, and has an available 5-V supply.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 V+ R1 VBIAS R2 2N3904 AOUT 8–Bits DAC TSC2301 VDD ARNG RRNG Figure 72. DAC Circuit When Using V+ Higher Than Vsupply.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 OPERATION - KEYPAD INTERFACE The TSC2301 contains a keypad interface that is suitable for use with matrix keypads up to 4 x 4 keys. A control register, the keypad control register, is used to set the scan rate for the keypad and de-bounce times. There is also a keypad mask register which allows certain keys to be masked from being read, or from causing the TSC2301 to detect a key-press on selected keys.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 AUDIO CODEC Audio Analog I/O The TSC2301 has one pair of stereo inputs, LLINEIN and RLINEIN, and one mono audio input, MICIN. The part also has one pair of stereo line outputs capable of driving a 10-kΩ load, VOUTL and VOUTR, as well as a stereo headphone output amplifier capable of driving a 16-Ω load at up to 30 mW/channel, HPL and HPR.
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TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 FO RM AT 3 D A C : 2 0 –B i t , M S B –F i r s t , I 2 S L –c h LRCIN R –c h BCKIN I2SDIN 1 2 3 18 19 20 M SB A D C : 2 0 –B it , M S B –F i r s t , 1 LSB 2 3 18 19 20 M SB LSB I2 S L –c h LRCIN R –c h BCKIN I2SDOUT 1 2 3 18 19 20 M SB 1 LS B 2 3 18 19 20 M SB LSB Figure 75. Audio Data Input/Output Format t LRP 0.5V DD LRCIN t BL t BCH t LB t BCL BCKIN 0.5V DD t BCY t DIS t DIH I2SDIN 0.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 29.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Audio Data Converters The TSC2301 includes a stereo 20-bit audio DAC and a stereo 20-bit audio ADC. The DAC and ADC are both capable of operating at 8 kHz, 11.025 kHz, 12 kHz, 16 kHz, 22.05 kHz, 24 kHz, 32 kHz, 44.1 kHz, or 48 kHz. The DAC and ADC must operate at the same sampling rate. When the ADC or DAC is operating, the part requires an audio MCLK input, which should be synchronous to the I2S bus clock.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Stereo DAC Overview The stereo DAC consists of a digital block to implement digital interpolation filter, volume control, de-emphasis filter and programmable digital effects/bass-boost filter for each channel. These are followed by a fifth-order single-bit digital delta-sigma modulator, and switched capacitor analog reconstruction filter.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 N0 = N3 = 27618 D1 = D4 = 32130 N1 = N4 = -27033 D2 = D5 = -31505 N2 = N5 = 26461 which implements the bass-boost transfer function shown in Figure 77, having a 3-dB attenuation for signals above approximately 150 Hz when operating at a 48-kHz sampling rate. All coefficients are represented by 16-bit twos complement integers with values ranging from -32768 to 32767. Default Bass-Boost Transfer Function 48 kHz Mode 0 –0.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 The ADC modulator and digital filter operate on a clock that changes directly with Fs. This is in contrast to the DAC, which keeps the modulator running at a high rate of 128 x 44.1 kHz or 128 x 48 kHz even if the incoming data rate is much lower, such as 8 kHz. Group delay of the ADC path varies with sampling frequency and is given by 28.7/Fs. Audio ADC SNR performance is 88-dB-A typical over 20-Hz - 20-kHz bandwidth in 44.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 30.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [13:12] — INML1-INML0 Left Audio ADC Input Multiplexer. These two bits select the analog input for the left channel ADC. The input to the left channel ADC can come from the microphone input, right line input, left line input, or from a mono mix of the left and right line inputs. The default input to the left channel ADC is the microphone input. Table 32.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [7:6] — MCLK1-MCLK0 Master Clock Ratio. These two bits select the ratio of the audio master clock frequency to the audio sampling frequency. The ratio can be 256 Fs, 384 Fs, or 512 Fs. The default master clock frequency is 256 Fs. Table 35.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 15 — ADMUL Left ADC Mute. This bit is used to mute the input to the left channel ADC volume control. The user can set this bit to mute the ADC while retaining the previous gain setting in ADVL[6:0], so that the PGA returns to the previous gain setting when ADMUL is cleared. When the ADMUL bit is set, the left ADC PGA soft-steps down to its lowest level, then mutes.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 The DAC volume control register is formatted as follows: Bit 15 MSB Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 DAMU L DAVL DAVL5 DAVL4 DAVL3 DAVL DAVL DAVL 6 2 1 0 Bit 7 DAMU R Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 LSB DAVR6 DAVR5 DAVR4 DAVR3 DAVR2 DAVR DAVR 1 0 Bit 15 — DAMUL Left DAC Mute. This bit is used to mute the input to the left channel DAC.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 ANALOG AUDIO BYPASS PATH VOLUME CONTROL REGISTER (Page 02, Address 03h) The bypass path volume control register controls the independent programmable gain amplifiers (PGA's) on the left and right channel analog audio bypass paths of the TSC2301. These bypass paths direct the line inputs directly to the line and headphone outputs entirely in the analog domain, with no A/D or D/A conversion.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [6:0] — BPVR6- BPVR0 Right Channel Audio Bypass Path Volume Control. These 7 bits control the gain setting of the right channel bypass path volume control PGA. This volume control can be programmed from -35.5 dB to +12 dB in 0.5-dB steps. Full volume (+12 dB) corresponds to a setting of 7Fh. Unity gain (0 dB) corresponds to 67h. Full attenuation (-35.5 dB) corresponds to 20h.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits [14:12] — KCAM2-KCAM0 Keyclick Amplitude. These bits set the amplitude of the keyclick sound with eight amplitude levels provided. KCAM[2:0] = 100 = Medium amplitude (default) KCAM[2:0] = 111 = Maximum amplitude KCAM[2:0] = 000 = Minimum amplitude Bit 11 — RESERVED This bit is reserved, and should be written to 0. If read, it reads back as 0. Bits [10:8] — KCFR2-KCFR0 Keyclick Frequency.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 1 — SSRTE Volume Soft-stepping Rate Select. This bit selects the speed of the soft-stepping function of the TSC2301 volume controls. At normal speed, the actual volume is updated approximately once every 20 µs. At half speed, the actual volume is updated approximately once every 40 µs. Table 47. Volume Soft-Stepping Rate Select SSRTE Description 0 Normal step rate used (default). 1 Half step rate used.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bit 11 — MOPD Mono Driver Power Down. This is used to power up (set to 0) or power down (set to 1) the mono output driver. If only playback of the line or Mic inputs through the mono output is needed, the user need only power up the mono section, and not the DAC or ADCs. The line inputs, Mic preamp, left channel ADC multiplexer and left channel volume control all power up if the mono output is powered up. The default is 1 (powered down).
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Table 52. Oscillator Clock Buffer Control BCKC Description 0 The output clock buffer is off (default). 1 The output clock buffer is on. Bit 3 — SMPD Synchronization Monitor Power Down. This bit turns ON/OFF the I2S bus sync monitor. Table 53. Synchronization Monitor Power Down SMPD Description 0 The I2S bus sync monitor is on (default). 1 The I2S bus sync monitor is off. Bit 2 — OTSYN I2S Out Of Sync.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 Bits 15,14 — RESERVED These bits are reserved and should be written to 0. If read, they read back as 0. Bits [13:8] — IO5- IO0 GPIO Directional Control. These 6 bits control the direction of the TSC2301s six GPIO pins. When one of these bits is set to one, the corresponding GPIO pin is configured as an output. When one of these bits is set to zero, the corresponding GPIO pin is configured as an input.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 AUDIO CLOCK CONFIGURATION REGISTER (Page 02, Address 1Bh) This register allows the user to use the output of the crystal oscillator as MCLK, and receive the PLL output on the PENIRQ pin.
TSC2301 www.ti.com SLAS371D – SEPTEMBER 2002 – REVISED AUGUST 2004 As described earlier, the audio common-mode voltage VCM is derived directly through an internal resistor divider between AVDD and AGND. Therefore, noise that couples onto AVDD/AGND is translated onto VCM and can adversely impact audio performance. The reference pins for the audio data converters, VREF+/VREF-, should also be kept as clean and noise-free as possible, since noise here affects audio DAC/ADC quality.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 26-Aug-2013 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TSC2301IPAGR TSC2301IZQZR Package Package Pins Type Drawing TQFP BGA MI CROSTA R JUNI OR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant PAG 64 1500 330.0 24.4 13.0 13.0 1.5 16.0 24.0 Q2 ZQZ 120 2500 330.0 16.4 6.3 6.3 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TSC2301IPAGR TQFP TSC2301IZQZR BGA MICROSTAR JUNIOR PAG 64 1500 367.0 367.0 45.0 ZQZ 120 2500 336.6 336.6 28.
MECHANICAL DATA MTQF006A – JANUARY 1995 – REVISED DECEMBER 1996 PAG (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 48 0,08 M 33 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 1,05 0,95 0°– 7° 0,75 0,45 Seating Plane 0,08 1,20 MAX 4040282 / C 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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