! " Data Manual August 2007 MSDS Bus Solutions SLLS442E
TUSB2136 Data Manual Universal Serial Bus Compound Hub with General-Purpose 8052 MCU Literature Number: SLLS442E August 2007 Printed on Recycled Paper
Contents Section 1 2 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Terminal Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . . . . . .
2.6.1 2.6.2 2.6.3 2.6.4 2.6.5 2.6.6 3 4 5 iv FUNADR: Function Address Register . . . . . . . . . . . . . . . . . USBSTA: USB Status Register . . . . . . . . . . . . . . . . . . . . . . . USBMSK: USB Interrupt Mask Register . . . . . . . . . . . . . . . USBCTL: USB Control Register . . . . . . . . . . . . . . . . . . . . . . HUBCNFG: HUB-Configuration Register . . . . . . . . . . . . . . . HUBPOTG: HUB Power-On to Power-Good Descriptor Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations Figure Title 1−1 TUSB2136 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−1 MCU Memory Map (TUSB2136B) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−2 Reset Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2−3 Pullup Resistor Connect/Disconnect Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . 2−4 Internal Vector Interrupt (INT0) . . . . . .
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1 Introduction The TUSB2136 is an integrated universal serial bus (USB) hub with a general-purpose 8052 microcontroller that can be used for various USB controller applications. The TUSB2136 has 8K × 8 RAM space for application development. Using a 12-MHz crystal, the onboard oscillator generates the internal system clocks. No additional programming is required for any part of the hub functions.
1.2 Functional Block Diagram 12 MHz Clock, PLL and Dividers USB0 USB1 Reset and Interrupt Logic 8052 Core USB HUB 6K y 8 ROM 8 8K y 8 SRAM 8 8 USB2 RSTI INT1 2 y 16-Bit Timers Port-1 8 P0[7:0] Port-2 8 P1[7:0] Port-3 8 P2[7:0] Port-4 8 P3[7:0] 8 USB SIE 8 CPU − I/F Susp/Res 8 UBM USB Buffer Manager 8 8 TDM Control Logic Figure 1−1.
1.3 Terminal Assignments P0.5 P0.4 P0.3 P0.2 P0.1 P0.0 GND P1.7 P1.6 VCC VREN VDD18 P1.5 P1.4 P1.3 P1.2 PM PACKAGE (TOP VIEW) 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 49 50 31 51 30 52 29 53 28 54 27 55 26 56 25 57 24 58 23 59 22 60 21 61 20 62 19 63 18 1 2 3 4 5 17 6 7 8 9 10 11 12 13 14 15 16 P1.1 P1.0 P2.7 P2.6 P2.5 P2.4 P2.3 P2.2 GND P2.1 P2.0 SELF/BUS GND DM0 DP0 PUR OVCR1 GND DM1 DP1 S2 S3 VCC SDA SCL RST TEST0 TEST1 SUSP 64 OVCR2 PWR02 PWR01 P0.6 P0.
1.5 Terminal Functions TERMINAL NAME NO.
1.5 Terminal Functions (Continued) TERMINAL NAME VCC VDD18† I/O NO. 10,39,62 — 37 DESCRIPTION Power supply input, 3.3 V typical 1.8 V. When VREN is low, 1.8 V must be applied to provide current for the core during suspend. VREN 38 I Voltage regulator enable: enable active LOW; disable active HIGH X2 60 O 12-MHz crystal output X1 61 I 12-MHz crystal input † During normal operation, the internal 3.3- to 1.8-V voltage regulator of the TUSB2136 is enabled and provides power to the core.
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2 Functional Description 2.1 MCU Memory Map Figure 2−1 illustrates the MCU memory map under boot and normal operation. It must be noted that the internal 256 bytes of IDATA are not shown since it is assumed to be in the standard 8052 location (0000 to 00FF). The shaded areas represent the internal ROM/RAM. For more information regarding the integrated 8052, see the TUSBxxxx Microcontroller Reference Guide (SLLU044).
I2C bus, or the host can be used via the USB. On device reset, the SDW bit (in the ROM register) and the CONT bit in the USB control register (USBCTL) are cleared. This configures the memory space to boot mode (see memory map, Table 2−2) and keeps the device disconnected from the host. The first instruction is fetched from location 0000 (which is in the 6K ROM). The 8K RAM is mapped to XDATA space (location 0000h).
2.2.4 INTCFG: Interrupt Configuration 7 6 5 4 3 2 1 0 RSV RSV RSV RSV I3 I2 I1 I0 R/O R/O R/O R/O R/W R/W R/W R/W BIT NAME RESET FUNCTION 0−3 I[3:0] 0010 The MCU can write to this register to set the interrupt delay time for port 2 on the MCU. The value of the lower nibble represents the delay in ms. Default after reset is 2 ms. 4−7 RSV 0 2.2.5 Reserved WDCSR: Watchdog Timer, Control, and Status Register A watchdog timer (WDT) with 1-ms clock is provided.
2.2.6 PCON: Power Control Register (at SFR 87h) 7 6 5 4 3 2 1 0 SMOD RSV RSV RSV GF1 GF0 RSV IDL R/W R/O R/O R/O R/W R/W R/O R/W BIT NAME RESET 0 IDL 0 FUNCTION MCU idle mode bit. This bit can be set by the MCU and is cleared only by the INT1 interrupt. IDL = 0 The MCU is not in idle mode. This bit is cleared by the INT1 interrupt logic when INT1 is asserted for at least 400 µs. IDL = 1 The MCU is in idle mode and RAM is in low-power mode.
Table 2−2.
Table 2−3.
Table 2−4 illustrates the EDB entries for EDB-1 to EDB-3. EDB-0 registers are described separately. Table 2−4. EDB Entries in RAM (n = 1 to 3) Offset 2.4.
2.4.3 7 6 5 4 3 2 1 0 NAK R/W C6 R/W C5 R/W C4 R/W C3 R/W C2 R/W C1 R/W C0 R/W BIT NAME RESET 6−0 C[6:0] x X-buffer byte count: 000 0000b ³ Count = 0 000 0001b ³ Count = 1 byte L 011 1111b ³ Count = 63 bytes 100 0000b ³ Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results. 7 NAK x NAK= 0 No valid data in buffer. Ready for host out NAK= 1 Buffer contains a valid packet from host (host-out request is NAK) 2.4.
2.4.6 OEPSIZXY_n: Output Endpoint X-/Y-Byte Count (n = 1 to 3) 7 6 5 4 3 2 1 0 RSV R/O S6 R/W S5 R/W S4 R/W S3 R/W S2 R/W S1 R/W S0 R/W BIT NAME RESET 6−0 S[6:0] x X- and Y-buffer size: 000 0000b ³ Count = 0 000 0001b ³ Count = 1 byte L 011 1111b ³ Count = 63 bytes 100 0000b ³ Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results. 7 RSV x Reserved = 0 2.4.
2.4.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) 7 6 5 4 3 2 1 0 NAK R/W C6 R/W C5 R/W C4 R/W C3 R/W C2 R/W C1 R/W C0 R/W BIT NAME RESET 6−0 C[6:0] x X-buffer byte count: 000 0000b ³ Count = 0 000 0001b ³ Count = 1 byte L 011 1111b ³ Count = 63 bytes 100 0000b ³ Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results. FUNCTION 7 NAK x NAK = 0 Buffer contains a valid packet for host-in transaction NAK = 1 Buffer is empty (host-in request is NAK) 2.4.
2.4.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) 7 6 5 4 3 2 1 0 RSV R/O S6 R/W S5 R/W S4 R/W S3 R/W S2 R/W S1 R/W S0 R/W BIT NAME RESET 6−0 S[6:0] x X- and Y-buffer size: 000 0000b ³ Count = 0 000 0001b ³ Count = 1 byte L 011 1111b ³ Count = 63 bytes 100 0000b ³ Count = 64 bytes Any value ≥ 100 0001b produces unpredictable results. FUNCTION 7 RSV x Reserved = 0 2.
2.5.2 7 6 5 4 3 2 1 0 NAK RSV RSV RSV R/W R/O R/O R/O C3 R/W C2 R/W C1 R/W C0 R/W BIT NAME RESET 3−0 C[3:0] 0000 6−4 RSV 0 Reserved = 0 7 NAK 1 NAK= 0 Buffer contains a valid packet for host-in transaction. NAK= 1 Buffer is empty (host-in request is NAK). 2.5.3 FUNCTION Byte count: 0000b ³ Count = 0 L 0111b ³ Count = 7 1000b ³ Count = 8 1001b to 1111b are reserved.
2.5.4 OEPBCNT_0: Output Endpoint-0 Byte Count Register 7 6 5 4 3 2 1 0 NAK RSV RSV RSV R/W R/O R/O R/O C3 R/W C2 R/W C1 R/W C0 R/W BIT NAME RESET 3−0 C[3:0] 0000 FUNCTION 6−4 RSV 0 Reserved = 0 7 NAK 1 NAK= 0 No valid data in buffer. Ready for host out NAK= 1 Buffer contains a valid packet from the host (NAK the host). Byte count: 0000b ³ Count = 0 L 0111b ³ Count = 7 1000b ³ Count = 8 1001b to 1111b are reserved. (If used, defaults to 8) 2.6 USB Registers 2.6.
2.6.2 USBSTA: USB Status Register All bits in this register are set by the hardware and are cleared by the MCU when writing a 1 to the proper bit location (writing a 0 has no effect). In addition, each bit can generate an interrupt if its corresponding mask bit is set (R/C notation indicates read and clear only by the MCU). 7 6 5 4 3 2 1 0 RSTR SUSR RESR PWOFF PWON SETUP RSV STPOW R/C R/C R/C R/C R/C R/C R/O R/C NAME RESET FUNCTION 0 SETUP overwrite bit.
2.6.
2.6.4 USBCTL: USB Control Register Unlike the other registers, this register is cleared by the power-up-reset signal only. The USB reset cannot reset this register (see the reset diagram in Figure 2−2). 7 6 5 4 3 2 1 0 CONT U1/2 RWUP FRSTE RWE B/S SIR DIR R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 0 DIR 0 As a response to a setup packet, the MCU decodes the request and sets or clears this bit to reflect the data transfer direction.
2.6.5 7 HUBCNFG: Hub Configuration Register 6 5 4 OCP I/G P3.1 P3.0 P2A P2E P1A P1E R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 0 P1E 0 1 2 3 P1A P2E P2A 0 0 0 3 2 1 0 FUNCTION Hub port-1 enable/disable control bit P1E = 0 Port 1 is disabled. P1E = 1 Port 1 is enabled. Hub port−1; permanent attachment control bit. P1A = 0 Port 1 is connected to a removable function. P1A = 1 Port 1 is connected to a permanent attachment function.
2.6.8 HUBPIDL: Hub PID Register (Low-Byte) 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 7−0 D[7:0] 00h 2.6.9 7 FUNCTION Hub PID low-byte value HUBPIDH: Hub PID Register (High-Byte) 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 7−0 D[15:8] 00h FUNCTION Hub PID high-byte value 2.6.
Table 2−6. External Pins Mapping to S[3:0] in VIDSTA Register VIDSTA REGISTER PIN COMMENTS S[3:0] NO. NAME S0 58 P3.0 Dual function, P3.0 I/O or S0 input S1 57 P3.1 Dual function, P3.1 I/O or S1 input S2 8 S2 S2-pin is input S3 9 S3 S3-pin is input 2.7 Function Reset and Power-Up Reset Interconnect Figure 2−2 represents the logical connection of USB-function reset (USBR) and power-up reset (RST) pins.
CMOS PUR 1.5 kΩ TUSB2046B HUB CONT-Bit D+ DP0 D− DM0 15 kΩ 15 kΩ TUSB2136 Figure 2−3. Pullup Resistor Connect/Disconnect Circuit 2.9 8052 Interrupt and Status Registers All seven 8052-standard interrupt sources are preserved. SIE is the standard interrupt enable register, which controls the seven interrupt sources. All the additional interrupt sources are connected together as an OR to generate INT0. The INT0 signal is provided to interrupt the MCU (see interrupt connection diagram, Figure 2−4).
2.9.1 8052 Standard Interrupt Enable Register 7 6 5 4 3 2 1 0 EA RSV ET2 ES ET1 EX1 ET0 INT0 R/W R/O R/O R/W R/W R/W R/W R/W BIT NAME RESET 0 INT0 0 1 2 3 4 5 ET0 EX1 ET1 ES ET2 0 0 0 0 0 6 RSV 0 7 EA 0 2.9.2 FUNCTION Enable or disable external interrupt-0 EX0 = 0 External interrupt-0 is disabled. EX0 = 1 External interrupt-0 is enabled. Enable or disable timer-0 interrupt ET0 = 0 Timer-0 interrupt is disabled.
2.9.3 VECINT: Vector Interrupt Register This register contains a vector value identifying the internal interrupt source that trapped to location 0003h. Writing any value to this register removes the vector and updates the next vector value (if another interrupt is pending). Note that the vector value is offset. Therefore, its value is in increments of two (bit 0 is set to 0). When no interrupt is pending, the vector is set to 00h. Table 2−8 is a table of the vector interrupt values.
2.9.4 Logical Interrupt Connection Diagram (INT0) Figure 2−4 represents the logical connection of the interrupt sources and the relation of the logical connection with INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hard wired. Vector 46h is the highest and 12h is the lowest. Table 2−8 lists the interrupt source for each valid interrupt vector.
2.10 I2C Registers The TUSB2136 only supports a master-slave relationship; therefore, it does not support bus arbitration. 2.10.1 I2CSTA: I2C Status and Control Register This register is used to control the stop condition for read and write operations. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits.
2.10.2 I2CADR: I2C Address Register This register holds the device address and the read/write command bit. 7 6 5 4 3 2 1 0 A6 R/W A5 R/W A4 R/W A3 R/W A2 R/W A1 R/W A0 R/W R/W BIT NAME RESET 0 R/W 0 7−1 A[6:0] 0000000 R/W FUNCTION Read/write command bit. R/W = 0 Write operation R/W = 1 Read operation Seven address bits for device addressing 2.10.3 I2CDAI: I2C Data-Input Register This register holds the received data from an external device.
• The TXE bit in I2CSTA is cleared, indicating busy. • The content of the I2CADR register is transmitted to the EEPROM (preceded by start condition on SDA). • The content of the I2CDAO register is transmitted to the EEPROM (EEPROM address). • The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been transmitted. • No stop condition is generated. EEPROM [low byte] • The MCU writes the low byte of the EEPROM address into the I2CDAO register.
• The RXF bit in I2CSTA is set, and interrupts the MCU, indicating that data is available. • The MCU reads the I2CDAI register, clearing the RXF bit (I2CSTA[RXF] = 0). • This operation repeats 31 times. 3. Last-Byte Read (byte 32) • The MCU sets I2CSTA[SRD] = 1. This forces the I2C controller to generate a stop condition after the I2CDAI register is received. • Data from the device is latched into the I2CDAI register (stop condition is transmitted).
EEPROM [DATA] • The MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the content of the I2CDAO register is transmitted. • The MCU writes the DATA to be written to the EEPROM into the I2CDAO register. • The TXE bit in I2CSTA is cleared, indicating busy. • The content of the I2CDAO register is transmitted to the device (EEPROM data). • The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been transmitted.
Last Byte EEPROM [DATA] • The MCU sets I2CSTA[SWR] = 1. This forces the I2C controller to generate a stop condition after the content of the I2CDAO register is transmitted. • The MCU writes the last DATA byte to be written to the EEPROM into the I2CDAO register. • The TXE bit in I2CSTA is cleared, indicating busy. • The content of the I2CDAO register is transmitted to the EEPROM (EEPROM data). • The TXE bit in I2CSTA is set, and interrupts the MCU, indicating that the I2CDAO register has been sent.
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3 Electrical Specifications 3.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . .
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4 Application 4.1 Keyboard Section Table 4−1 outlines the GPIO assignment for the switch-matrix scanning and for keyboard LED drive. Figure 4−1 illustrates the port-3 pins that are assigned to drive the four keyboard LEDs. As shown, P3[5:2] can sink up to 12 mA (open-drain output) on each pin. Figure 4−2 illustrates the 18 outputs (open-drain) and the 8 inputs (internal pullups) that are used for the switch-matrix scanning. Figure 4−3 illustrates the partial connection bus power mode.
TUSB2136 18 × 8 Matrix 8 P0[7:0] 8 P1[7:0] 1 P3.6 1 P3.7 8 P2[7:0] Figure 4−2. Keyboard Matrix Scan Connection C5 C4 VCC TPS76333 5V X1 VR C1 C2 R4 X2 VCC SCL VCC SDA C3 R1 I2C EEPROM R5 TUSB2136 VCC Vreg R2 VREN SUSP PWR OVCR R3 PS TPS2042 Figure 4−3. Partial Connection Bus Power Mode PUR Bus PWR (5 V) 3.3 V 1.5 kΩ 1.5 kΩ D+ DP0 D+ DP0 D− DM0 D− DM0 (a) (b) Figure 4−4.
5V To Power Switch R1 DP1 D+ R2 DM1 D− 15 kΩ 15 kΩ GND Figure 4−5. Downstream Connection − Only One Port Shown 4.2 Reset Timing There are two requirements for the reset signal timing. First, the reset window should be between 100 ms and 10 ms. At power up, this time is measured from the time the power ramps up to 90% of the nominal VCC until the reset signal goes high (above 1.2 V). The second requirement is that the clock has to be valid during the last 60 ms of the reset window.
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PACKAGE OPTION ADDENDUM www.ti.com 20-Mar-2008 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Drawing Pins Package Eco Plan (2) Qty TUSB2136PM ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR TUSB2136PMG4 ACTIVE LQFP PM 64 160 Green (RoHS & no Sb/Br) CU NIPDAU Level-3-260C-168 HR Lead/Ball Finish MSL Peak Temp (3) (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
MECHANICAL DATA MTQF008A – JANUARY 1995 – REVISED DECEMBER 1996 PM (S-PQFP-G64) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 0,08 M 33 48 49 32 64 17 0,13 NOM 1 16 7,50 TYP Gage Plane 10,20 SQ 9,80 12,20 SQ 11,80 0,25 0,05 MIN 0°– 7° 0,75 0,45 1,45 1,35 Seating Plane 0,08 1,60 MAX 4040152 / C 11/96 NOTES: A. B. C. D. All linear dimensions are in millimeters. This drawing is subject to change without notice.
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