Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsMicrocontrollers, Microprocessors & QuartzesEmbedded microcontroller (user-defined) TUSB3410 USB serial port controller VFQFN 32

TUSB3410, TUSB3410I

USB to Serial Port Controller

January 2010 Connectivity Interface Solutions

Data Manual

SLLS519H

Summary of content (98 pages)

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TUSB3410, TUSB3410I USB to Serial Port Controller Data Manual January 2010 Connectivity Interface Solutions SLLS519H
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Contents Contents Section 1 2 3 4 Page Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Ordering Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.
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Contents Section 5 6 7 iv Page USB Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.1 FUNADR: Function Address Register (Addr:FFFFh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.2 USBSTA: USB Status Register (Addr:FFFEh) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.3 USBMSK: USB Interrupt Mask Register (Addr:FFFDh) . . . . . . .
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Contents Section Page 7.2 48 48 49 49 49 50 50 51 51 51 53 53 53 53 54 55 57 57 57 58 58 58 58 59 59 60 61 63 63 63 64 64 65 66 66 66 68 68 69 69 69 69 69 71 72 UART Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.1 Receiver Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7.2.2 Hardware Flow Control . . . . . . . . . . . . . . . . . . . . .
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Contents Section 11.8 Page Built-In Vendor Specific USB Requests . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.1 Reboot . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.2 Force Execute Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11.8.3 External Memory Read . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Illustrations List of Illustrations Figure 1−1 1−2 3−1 3−2 3−3 4−1 5−1 5−2 7−1 7−2 7−3 9−1 11−1 11−2 13−1 13−2 13−3 Title Page Data Flow . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . USB-to-Serial (Single Channel) Controller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . RS-232 and IR Mode Select . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables List of Tables Table Title 2−1 4−1 4−2 4−3 4−4 4−5 4−6 4−7 6−1 6−2 7−1 7−2 7−3 7−4 9−1 9−2 11−1 11−2 11−3 11−4 11−5 11−6 11−7 11−8 11−9 11−10 11−11 Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ROM/RAM Size Definition Table . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . XDATA Space . . . . . . . . . . . . . . . . . . . .
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Introduction 1 Introduction 1.1 Controller Description The TUSB3410 provides bridging between a USB port and an enhanced UART serial port. The TUSB3410 contains all the necessary logic to communicate with the host computer using the USB bus. It contains an 8052 microcontroller unit (MCU) with 16K bytes of RAM that can be loaded from the host or from the external on-board memory via an I2C bus. It also contains 10K bytes of ROM that allow the MCU to configure the USB port at boot time.
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Introduction 12 MHz Clock Oscillator PLL and Dividers DP, DM 8052 Core 24 MHz 10K × 8 ROM USB TxR 16K × 8 RAM 2K × 8 SRAM 8 8 2 × 16-Bit Timers 8 8 4 Port 3 8 8 I2C Controller P3.4 P3.3 P3.1 P3.0 I2C Bus 8 USB Serial Interface Engine CPU-I/F Suspend/ Resume DMA-1 DMA-3 8 8 8 UBM USB Buffer Manager 8 RTS CTS DTR DSR UART−1 SIN SOUT TDM Control Logic IR Encoder M U X M U X SOUT/IR_SOUT IR Decoder SIN/IR_SIN Figure 1−2.
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Introduction 1.2 Ordering Information PACKAGED DEVICES TA 32-TERMINAL LQFP PACKAGE 32-TERMINAL QFN PACKAGE TUSB3410 I VF TUSB3410 I RHB 40°C to 85°C −40°C TUSB3410 I RHBR TUSB3410 VF 0°C to 70°C 1.3 Version TUSB3410 RHB TUSB3410 RHBR COMMENT Industrial temperature range Shipped in trays Industrial temperature range Tape and Reel Option Shipped in trays Tape and Reel Option Revision History Date Changes Mar−2002 Initial Release A Apr−2002 1. 2. 3. 4.
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Introduction 4 TUSB3410, TUSB3410I SLLS519H—January 2010
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Main Features 2 Main Features 2.1 USB Features • Fully compliant with USB 2.0 full speed specifications: TID #40340262 • Supports 12-Mbps USB data rate (full speed) • Supports USB suspend, resume, and remote wakeup operations • Supports two power source modes: • 2.2 Bus-powered mode − Self-powered mode Can support a total of three input and three output (interrupt, bulk) endpoints General Features • 2.
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Main Features 2.4 • Line break generation and detection • Internal test and loop-back capabilities • Modem-control functions (CTS, RTS, DSR, DTR, RI, and DCD) • Internal diagnostics capability − Loopback control for communications link-fault isolation − Break, parity, overrun, framing-error simulation Terminal Assignment TEST1 TEST0 CLKOUT DTR RTS SOUT/IR_SOUT GND SIN/IR_SIN VF PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 VCC X2 X1/CLKI GND P3.4 P3.3 P3.1 P3.
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Main Features Table 2−1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION CLKOUT 22 O Clock output (controlled by bits 2 (CLKOUTEN) and 3(CLKSLCT) in the MODECNFG register (see Section 5.
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Main Features 8 TUSB3410, TUSB3410I SLLS519H—January 2010
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Detailed Controller Description 3 Detailed Controller Description 3.1 Operating Modes The TUSB3410 controls its USB interface in response to USB commands, and this action is independent of the serial port mode selected. On the other hand, the serial port can be configured in three different modes. As with any interface device, data movement is the main function of the TUSB3410, but typically the initial configuration and error handling consume most of the support code.
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Detailed Controller Description 3.5.1 RS-232 Data Mode The default mode is called the RS-232 mode and is typically used for full duplex communication on SOUT and SIN. In this mode, the modem control outputs (RTS and DTR) communicate to a modem or are general outputs. The modem control inputs (CTS, DSR, DCD, and RI/CP) communicate to a modem or are general inputs. Alternatively, RTS and CTS (or DTR and DSR) can throttle the data flow on SOUT and SIN to prevent receive FIFO overruns.
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Detailed Controller Description SOUT 0 M U X From UART SOUT IR_TX IR Encoder SOUT/IR_SOUT Terminal 1 IREN (in USBCTL Register) 0 UART BaudOut Clock SOFTSW (in MODECNFG Register) M U X 1 TXCNTL (in MODECNFG Register) 0 M U X 3.556 MHz 1 CLKSLCT (in MODECNFG Register) CLKOUT Terminal CLKOUTEN (in MODECNFG Register) 3.3 V 0 To UART Receiver SIN M U X 1 IR_RX IR Decoder SIN/IR_SIN Terminal Figure 3−1.
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Detailed Controller Description DB9 Connector 12 MHz Transceivers X1/CLKI X2 DTR 4 RTS 7 RI/CP DP DM USB-0 DCD 1 DSR 6 CTS 8 SOUT 3 SIN 2 Serial Port TUSB3410 P3.0 P3.1 P3.3 P3.4 GPIO Terminals for Other Onboard Control Function Figure 3−2. USB-to-Serial Implementation (RS-232) 12 MHz X1/CLKI RTS RS-485 Bus X2 SOUT DTR SIN DP DM USB-0 TUSB3410 RS-485 Transceiver 2-Bit Time 1-Bit Max SOUT DTR RTS Receiver is Disabled if RCVE = 0 Figure 3−3.
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MCU Memory Map 4 MCU Memory Map Figure 4−1 illustrates the MCU memory map under boot and normal operation. NOTE: The internal 256 bytes of RAM are not shown, since they are assumed to be in the standard 8052 location (0000h to 00FFh). The shaded areas represent the internal ROM/RAM. • When bit 0 (SDW) of the ROMS register is 0 (boot mode) The 10K ROM is mapped to address (0x0000−0x27FF) and is duplicated in location (0x8000−0xA7FF) in code space.
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MCU Memory Map 4.1 Miscellaneous Registers 4.1.1 ROMS: ROM Shadow Configuration Register (Addr:FF90h) This register is used by the MCU to switch from boot mode to normal operation mode (boot mode is set on power-on reset only). In addition, this register provides the device revision number and the ROM/RAM configuration. 7 6 5 4 3 2 1 0 ROA S1 S0 RSVD RSVD RSVD RSVD SDW R/O R/O R/O R/O R/O R/O R/O R/W BIT 0 NAME SDW RESET 0 FUNCTION This bit enables/disables boot ROM.
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MCU Memory Map and writes to the 16K RAM in XDATA space. If it does not contain the code, then the MCU proceeds to boot from the USB. Once the code is loaded, the MCU sets the SDW bit to 1 in the ROMS register. This switches the memory map to normal mode; that is, the 16K RAM is mapped to code space, and the MCU starts executing from location 0000h. Once the switch is done, the MCU sets the CONT bit to 1 in the USBCTL register.
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MCU Memory Map Table 4−3.
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MCU Memory Map Table 4−3.
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MCU Memory Map Table 4−4.
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MCU Memory Map Table 4−5. Endpoint Registers and Offsets in RAM (n = 1 to 3) OFFSET ENTRY NAME DESCRIPTION 07 EPSIZXY_n I/O endpoint_n: X/Y-buffer size 06 EPBCTY_n I/O endpoint_n: Y-byte count 05 EPBBAY_n I/O endpoint_n: Y-buffer base address 04 SPARE Not used 03 SPARE Not used 02 EPBCTX_n I/O endpoint_n: X-byte count 01 EPBBAX_n I/O endpoint_n: X-buffer base address 00 EPCNF_n I/O endpoint_n: Configuration Table 4−6.
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MCU Memory Map 4.3.3 OEPBCTX_n: Output Endpoint X Byte Count (n = 1 to 3) (Offset 2) 7 6 5 4 3 2 1 0 NAK C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME 6−0 7 RESET FUNCTION C[6:0] x X-buffer byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. NAK x NAK = 0 NAK = 1 No valid data in buffer.
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MCU Memory Map 4.3.6 OEPSIZXY_n: Output Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 7 6 5 4 3 2 1 0 RSV S6 S5 S4 S3 S2 S1 S0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 6−0 S[6:0] x X- and Y-buffer size: 0000.0000b Size = 0 0000.0001b Size = 1 byte : : 0011.1111b Size = 63 bytes 0100.0000b Size = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 RSV x Reserved = 0 4.3.
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MCU Memory Map 4.3.9 IEPBCTX_n: Input Endpoint X-Byte Count (n = 1 to 3) (Offset 2) 7 4 3 2 1 0 C6 C5 C4 C3 C2 C1 C0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME 7 4.3.10 RESET FUNCTION C[6:0] x X-Buffer byte count: X000.0000b Count = 0 X000.0001b Count = 1 byte : : X011.1111b Count = 63 bytes X100.0000b Count = 64 bytes Any value ≥ 100.0001b may result in unpredictable results.
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MCU Memory Map 4.3.12 IEPSIZXY_n: Input Endpoint X-/Y-Buffer Size (n = 1 to 3) (Offset 7) 7 6 5 4 3 2 1 0 RSV S6 S5 S4 S3 S2 S1 S0 R/W R/W R/W R/W R/W R/W R/W R/W NAME BIT RESET FUNCTION 6−0 S[6:0] x X- and Y-buffer size: 0000.0000b Size = 0 0000.0001b Size = 1 byte : : 0011.1111b Size = 63 bytes 0100.0000b Size = 64 bytes Any value ≥ 100.0001b may result in unpredictable results. 7 RSV x Reserved = 0 4.
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MCU Memory Map 4.4.2 IEPBCNT_0: Input Endpoint-0 Byte Count Register (Addr:FF81h) 7 6 5 4 3 2 1 0 NAK RSV RSV RSV C3 C2 C1 C0 R/W R/O R/O R/O R/W R/W R/W R/W BIT NAME 3−0 C[3:0] RESET 0h Byte count: 0000b Count = 0 : : 0111b Count = 7 1000b Count = 8 1001b to 1111b are reserved.
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USB Registers 5 USB Registers 5.1 FUNADR: Function Address Register (Addr:FFFFh) This register contains the device function address. 7 6 5 4 3 2 1 0 RSV FA6 FA5 FA4 FA3 FA2 FA1 FA0 R/O R/W R/W R/W R/W R/W R/W R/W RESET FUNCTION FA[6:0] NAME 0 These bits define the current device address assigned to the function. The MCU writes a value to this register because of the SET-ADDRESS host command. RSV 0 Reserved = 0 BIT 6−0 7 5.
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USB Registers 5.
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USB Registers 5.4 USBCTL: USB Control Register (Addr:FFFCh) Unlike the rest of the registers, this register is cleared by the power-up reset signal only. The USB reset cannot reset this register (see Figure 5−1). 7 6 5 4 3 2 1 0 CONT IREN RWUP FRSTE RSV RSV SIR DIR R/W R/W R/C R/W R/W R/W R/W R/W BIT NAME 0 RESET DIR 0 As a response to a setup packet, the MCU decodes the request and sets/clears this bit to reflect the data transfer direction.
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USB Registers Clock Output Control Bit 2 (CLKOUTEN) in the MODECNFG register enables or disables the clock output at the CLKOUT terminal of the TUSB3410. The power up default of CLKOUT is disabled. Firmware can write a 1 to enable the clock output if needed. Bit 3 (CLKSLCT) in the MODECNFG register selects the output clock source from either a fixed 3.556-MHz free-running clock or the UART BaudOut clock. 5.
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USB Registers 5.8 SERNUM6: Device Serial Number Register (Byte 6) (Addr:FFEEh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM6) contains byte 6 of the complete 64-bit device serial number. This register cannot be reset.
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USB Registers 5.12 SERNUM2: Device Serial Number Register (Byte 2) (Addr:FFEAh) The device serial number registers mirror the unique 64-bit die id value. After power-up reset, this read-only register (SERNUM2) contains byte 2 of the complete 64-bit device serial number. This register cannot be reset.
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USB Registers 5.15 Function Reset And Power-Up Reset Interconnect Figure 5−1 represents the logical connection of the USB-function reset (USBR) signal and the power-up reset (RESET) terminal. The internal RESET signal is generated from the RESET terminal (PURS signal) or from the USB reset (USBR signal). The USBR can be enabled or disabled by bit 4 (FRSTE) in the USBCTL register (see Section 5.4) (on power up, FRSTE = 0).
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USB Registers 32 TUSB3410, TUSB3410I SLLS519H—January 2010
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DMA Controller 6 DMA Controller Table 6−1 outlines the DMA channels and their associated transfer directions. Two channels are provided for data transfer between the host and the UART. Table 6−1. DMA Controller Registers 6.
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DMA Controller 6.1.1 DMACDR1: DMA Channel Definition Register (UART Transmit Channel) (Addr:FFE0h) These registers define the EDB number that the DMA uses for data transfer to the UARTS. In addition, these registers define the data transfer direction and selects X or Y as the transaction buffer. 7 6 5 4 3 2 1 0 EN INE CNT XY T/R E2 E1 E0 R/W R/W R/W R/W R/O R/W R/W R/W BIT NAME RESET 2−0 FUNCTION E[2:0] 0 Endpoint descriptor pointer.
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DMA Controller 6.1.3 DMACDR3: DMA Channel Definition Register (UART Receive Channel) (Addr:FFE4h) These registers define the EDB number that the DMA uses for data transfer from the UARTS. In addition, these registers define the data transfer direction and selects X or Y as the transaction buffer. 7 6 5 EN INE CNT XY T/R E2 E1 E0 R/W R/W R/W R/W R/O R/W R/W R/W 3 2 1 0 RESET FUNCTION E[2:0] 0 Endpoint descriptor pointer.
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DMA Controller 6.1.4 DMACSR3: DMA Control And Status Register (UART Receive Channel) (Addr:FFE5h) This register defines the transaction time-out value. In addition, it contains a completion code that reports any errors or a time-out condition. 7 6 5 4 3 2 1 0 TEN C4 C3 C2 C1 C0 TXFT OVRUN R/W R/W R/W R/W R/W R/W R/C R/C BIT NAME RESET 0 OVRUN 0 1 TXFT 6−2 C[4:0] 7 FUNCTION Overrun condition bit.
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DMA Controller 6.2.1 IN Transaction (TUSB3410 to Host) 1. The MCU initializes the IEDB (64-byte packet, and double buffering is used) and the following DMA registers: • DMACSR3: Defines the transaction time-out value. • DMACDR3: Defines the IEDB being used and the DMA mode of operation (continuous mode). Once this register is set with EN = 1, the transfer starts. 2. The DMA transfers data from the UART to the X buffer.
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DMA Controller 6.2.2 OUT Transaction (Host to TUSB3410) 1. The MCU initializes the OEDB (64-byte packet, and double buffering is used) and the following DMA registers: • DMACSR1: Provides an indication of a partial packet. • DMACDR1: Defines the output endpoint being used, and the DMA mode of operation (continuous mode). Once the EN bit is set to 1 in this register, the transfer starts. 2. The UBM transfers data from host to X-buffer.
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UART 7 UART 7.1 UART Registers Table 7−1 summarizes the UART registers. These registers are used for data I/O, control, and status information. UART setup is done by the MCU. Data transfer is typically performed by the DMAC. However, the MCU can perform data transfer without a DMA; this is useful when debugging the firmware. Table 7−1.
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UART 7.1.3 LCR: Line Control Register (Addr:FFA2h) This register controls the data communication format. The word length, number of stop bits, and parity type are selected by writing the appropriate bits to the LCR.
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UART 7.1.4 FCRL: UART Flow Control Register (Addr:FFA3h) This register provides the flow-control modes of operation (see Table 7−3 for more details). 7 6 5 4 3 2 1 0 485E DTR RTS RXOF DSR CTS TXOA TXOF R/W R/W R/W R/W R/W R/W R/W R/W BIT 0 NAME TXOF RESET 0 FUNCTION This bit controls the transmitter Xon/Xoff flow control.
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UART 7.1.5 Transmitter Flow Control On reset (power up, USB, or soft reset) the transmitter defaults to the Xon state and the flow control is set to mode-0 (flow control is disabled). Table 7−2.
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UART 7.1.6 MCR: Modem-Control Register (Addr:FFA4h) This register provides control for modem interface I/O and definition of the flow control mode. 7 6 5 4 3 2 1 0 LCD LRI RTS DTR RSV LOOP RCVE URST R/W R/W R/W R/W R/W R/W R/W R/W BIT 0 1 2 NAME RESET URST RCVE LOOP 0 0 0 FUNCTION UART soft reset. This bit can be used by the MCU to reset the UART. URST = 0 Normal operation. Writing a 0 by MCU has no effect.
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UART 7.1.7 LSR: Line-Status Register (Addr:FFA5h) This register provides the status of the data transfer. DMA transfer is halted when any of bit 0 (OVR), bit 1 (PTE), bit 2 (FRE), or bit 3 (BRK) is 1. 7 6 5 4 3 2 1 0 RSV TEMT TxE RxF BRK FRE PTE OVR R/O R/O R/O R/O R/C R/C R/C R/C BIT 0 NAME OVR RESET 0 FUNCTION This bit indicates the overrun condition of the receiver. If set, it halts the DMA transfer and generates a status interrupt (if enabled).
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UART Device Terminals CTS DSR Modem Status Register Bit 4 LCTS RI/CP Bit 5 LDSR DCD Bit 6 LRI Bit 7 LCD FCRL Register Setting Modem Control Register Bit 4 DTR DTR Bit 5 RTS RTS Bit 6 LRI Bit 7 LCD Bit 2 LOOP FCRL Register Setting Figure 7−1.
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UART 7.1.8 MSR: Modem-Status Register (Addr:FFA6h) This register provides information about the current state of the control lines from the modem. 7 6 5 4 3 2 1 0 LCD LRI LDSR LCTS ΔCD TRI ΔDSR ΔCTS R/O R/O R/O R/O R/C R/C R/C R/C BIT NAME RESET FUNCTION 0 ΔCTS 0 This bit indicates that the CTS input has changed state. Cleared when the MCU writes a 1 to this bit. Writing a 0 has no effect. 1 ΔDSR 0 This bit indicates that the DSR input has changed state.
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UART 7.1.10 DLH: Divisor Register High Byte (Addr:FFA8h) This register contains the high byte of the baud-rate divisor. 7 6 5 4 3 2 1 0 D15 D14 D13 D12 D11 D10 D9 D8 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME 7−0 RESET D[15:8] 7.1.11 00h FUNCTION High-byte value of the 16-bit divisor for generation of the baud clock in the baud-rate generator. Baud-Rate Calculation The following formulas calculate the baud-rate clock and the divisors.
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UART 7.1.13 XOFF: Xoff Register (Addr:FFAAh) This register contains a value that is compared to the received data stream. Detection of a match halts the DMA transfer, and interrupts the MCU (only if the interrupt enable bit is set). This value is also used for Xoff transmission. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/W R/W R/W R/W R/W R/W R/W R/W 1 0 BIT NAME 7−0 RESET D[7:0] 7.1.
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UART Receiver Halt on Error or Time-Out 64-Byte Y-Buffer RDR: 32-Byte FIFO DMA DMACDR3 4 8 SIN 64-Byte X-Buffer RTS/DTR = 1 or Xoff Transmitted X/Y Host RTS/DTR = 0 or Xon Transmitted USB Buffer Manager Xoff/Xon CTS/DTR = 1/0 64-Byte Y-Buffer Pause/Run DMA DMACDR1 64-Byte X-Buffer SOUT TDR Figure 7−2. Receiver/Transmitter Data Flow 7.2.2 Hardware Flow Control Figure 7−3 illustrates the connection necessary to achieve hardware flow control.
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UART 7.2.5 Xon/Xoff Receiver Flow Control To enable Xon/Xoff flow control, certain bits within the modem control register must be set as follows: MCR bit 5 = 1 and MCR bits 6 and 7 = 00. In this mode, the Xon/Xoff bytes are transmitted to an external sending device to control the device’s transmission. When the high-level mark (of the FIFO) is reached, the Xoff byte is transmitted, signaling to an external sending device to halt its transfer.
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Expanded GPIO Port 8 Expanded GPIO Port 8.1 Input/Output and Control Registers The TUSB3410 has four general-purpose I/O terminals (P3.0, P3.1, P3.3, and P3.4) that are controlled by firmware running on the MCU. Each terminal can be controlled individually and each is implemented with a 12-mA push/pull CMOS output with 3-state control plus input.
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Expanded GPIO Port 52 TUSB3410, TUSB3410I SLLS519H—January 2010
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Interrupts 9 Interrupts 9.1 8052 Interrupt and Status Registers All 8052 standard, five interrupt sources are preserved. SIE is the standard interrupt-enable register that controls the five interrupt sources. This is also known as IE0 located at S:A8h in the special function register area. All the additional interrupt sources are ORed together to generate EX0. Table 9−1.
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Interrupts 9.1.3 VECINT: Vector Interrupt Register (Addr:FF92h) This register contains a vector value, which identifies the internal interrupt source that is trapped to location 0003h. Writing (any value) to this register removes the vector and updates the next vector value (if another interrupt is pending). Note: the vector value is offset; therefore, its value is in increments of two (bit 0 is set to 0). When no interrupt is pending, the vector is set to 00h (see Table 9−2).
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Interrupts 9.1.4 Logical Interrupt Connection Diagram (Internal/External) Figure 9−1 shows the logical connection of the interrupt sources and its relationship to INT0. The priority encoder generates an 8-bit vector, corresponding to 64 interrupt sources (not all are used). The interrupt priorities are hardwired. Vector 0x88 is the highest and 0x12 is the lowest. Interrupts Priority Encoder IEO Vector IEO (INT0) Figure 9−1.
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Interrupts 56 TUSB3410, TUSB3410I SLLS519H—January 2010
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I 2C Port I2C Port 10 10.1 I2C Registers 10.1.1 I2CSTA: I 2C Status and Control Register (Addr:FFF0h) This register controls the stop condition for read and write operations. In addition, it provides transmitter and receiver handshake signals with their respective interrupt enable bits. 7 6 5 4 3 RXF RIE R/O R/W 2 1 0 ERR 1/4 R/C R/W TXE TIE SRD SWR R/O R/W R/W R/W BIT NAME RESET FUNCTION 0 SWR 0 Stop write condition.
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I 2C Port 10.1.2 I2CADR: I 2C Address Register (Addr:FFF3h) This register holds the device address and the read/write command bit. 7 6 5 4 3 2 1 0 A6 A5 A4 A3 A2 A1 A0 R/W R/W R/W R/W R/W R/W R/W R/W R/W NAME BIT 0 RESET R/W 0 FUNCTION Read/write command bit R/W = 0 R/W = 1 7−1 A[6:0] 10.1.
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I 2C Port • The contents of the I2CDAO register are transmitted to EEPROM (EPROM address). • Bit 3 (TXE) in the I2CSTA register is set and interrupts the MCU, indicating that the I2CDAO register has been transmitted. • A stop condition is not generated. EPROM [Low Byte] • The MCU writes the low byte of the EEPROM address into the I2CDAO register. • Bit 3 (TXE) in the I2CSTA register is automatically cleared (indicates busy) by writing to the I2CDAO register.
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I 2C Port N-Byte Read (31 Bytes) • The data from the device is latched into the I2CDAI register (stop condition is not transmitted). • Bit 7 (RXF) in the I2CSTA register is set and interrupts the MCU, indicating that data is available. • The MCU reads the I2CDAI register. This clears bit 7 (RXF) in the I2CSTA register. • This operation repeats 31 times. Last-Byte Read (Byte 32) • MCU sets bit 1 (SRD) in the I2STA register to 1.
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I 2C Port 10.6 Page-Write Operation The page-write operation is initiated in the same way as byte write, with the exception that a stop condition is not generated after the first EPROM [DATA] is transmitted. The following describes the sequence of writing 32 bytes in page mode. Device Address + EPROM [High Byte] • The MCU clears bit 0 (SWR) in the I2CSTA register. This forces the I2C controller to not generate a stop condition after the contents of the I2CDAO register are transmitted.
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I 2C Port 62 TUSB3410, TUSB3410I SLLS519H—January 2010
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TUSB3410 Bootcode Flow 11 TUSB3410 Bootcode Flow 11.1 Introduction TUSB3410 bootcode is a program embedded in the 10k-byte boot ROM within the TUSB3410. This program is designed to load application firmware from either an external I2C memory device or USB host bootloader device driver. After the TUSB3410 finishes downloading, the bootcode releases its control to the application firmware. This section describes how the bootcode initializes the TUSB3410 device in detail.
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TUSB3410 Bootcode Flow If the descriptor block contains binary firmware, then the bootcode sets the header pointer to the beginning of the binary firmware in the I2C EEPROM. If the descriptor block is end of header, then the bootcode stops searching. • • Enable global and USB interrupts and set the connection bit to 1. − Enable global interrupts by setting bit 7 (EA) within the SIE register (see Section 9.1.1) to 1.
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TUSB3410 Bootcode Flow The bootcode uses 0x0451 (Texas Instruments) as the vendor ID and 0x3410 (TUSB3410) as the product ID. It also supports three different strings and one configuration. Table 11−1 lists the device descriptor. Table 11−1. Device Descriptor OFFSET (decimal) FIELD SIZE VALUE DESCRIPTION 0 bLength 1 0x12 1 bDescriptorType 1 1 2 bcdUSB 2 0x0110 4 bDeviceClass 1 0xFF 5 bDeviceSubClass 1 0 We have no subclasses. 6 bDeviceProtocol 1 0 We use no protocols.
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TUSB3410 Bootcode Flow 11.3.3 Interface Descriptor The interface descriptor provides the number of endpoints supported by this interface as well as interface class, subclass, and protocol. The bootcode supports only one endpoint and use its own class. Table 11−3 lists the interface descriptor. Table 11−3.
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TUSB3410 Bootcode Flow Table 11−5.
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TUSB3410 Bootcode Flow Table 11−5. String Descriptor (Continued) OFFSET SIZE VALUE 68 FIELD 2 ‘ ’,0x00 70 2 ‘D’,0x00 72 2 ‘e‘,0x00 74 2 ‘v’,0x00 76 2 ‘I,0x00 78 2 ‘c’,0x00 80 DESCRIPTION 2 ‘e’,0x00 82 bLength 1 34 (decimal) 84 bDescriptorType 1 0x03 86 bString 2 r0,0x00 UNICODE 88 2 r1,0x00 R0 to rF are BCD of SERNUM0 to 90 2 r2,0x00 SERNUM7 registers.
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TUSB3410 Bootcode Flow 11.4.2 Descriptor Block Each descriptor block contains a prefix and content. The size of the prefix is always 4 bytes. It contains the data type, size, and checksum for data integrity. The descriptor content contains the corresponding information specified in the prefix. It could be as small as 1 byte or as large as 65535 bytes. The next descriptor immediately follows the previous descriptor.
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TUSB3410 Bootcode Flow Table 11−6. USB Descriptors Header OFFSET TYPE SIZE VALUE 0 Signature0 1 0x10 FUNCTION_PID_L 1 Signature1 1 0x34 FUNCTION_PID_H 2 Data Type 1 0x03 USB device descriptor 3 Data Size (low byte) 1 0x12 The device descriptor is 18 (decimal) bytes.
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TUSB3410 Bootcode Flow Table 11−6. USB Descriptors Header (Continued) OFFSET TYPE SIZE VALUE 40 bAlternateSetting 1 0x00 Value used to select alternate setting for the interface identified in the prior field 41 bNumEndpoints 1 0x01 Number of endpoints used by this interface (excluding endpoint zero). If this value is zero, this interface only uses the default control pipe. 42 bInterfaceClass 1 0xFF The interface class is vendor specific.
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TUSB3410 Bootcode Flow Table 11−7.
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TUSB3410 Bootcode Flow 11.8.3 External Memory Read The bootcode returns the content of the specified address. 11.8.4 bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_IN 11000000b bRequest BTC_EXETERNAL_MEMORY_READ 0x90 wValue None 0x0000 wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength 1 byte 0x0001 Data Byte in the specified address 0xNN External Memory Write The external memory write command tells the bootcode to write data to the specified address.
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TUSB3410 Bootcode Flow 11.8.7 Internal ROM Memory Read The bootcode returns the byte of the specified address within the boot ROM. That is, the binary code of the bootcode. bmRequestType USB_REQ_TYPE_DEVICE | USB_REQ_TYPE_VENDOR | USB_REQ_TYPE_OUT 01000000b bRequest BTC_INTERNAL_ROM_MEMORY_READ 0x94 wValue None 0x0000 wIndex Data address 0xNNNN (From 0x0000 to 0xFFFF) wLength 1 byte 0x0001 Data Byte in the specified address 0xNN 11.9 Bootcode Programming Consideration 11.9.
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TUSB3410 Bootcode Flow Setup Stage Data Stage Setup (0) IN(1) More Packets IN(0) INT INT 1.Hardware generates interrupt to MCU. 2.Hardware sets NAK on both the IN and the OUT endpoints. 3.Set DIR bit in USBCTL to indicate the data direction. 4.Decode the setup packet. 5.If another setup packet arrives, abandon this one. 6.Execute appropriate routine per Table 11-9. a) Clear NAK bit in OUT endpoint. b) Copy data to IN endpoint buffer and set byte count. StatusStage IN(0/1) INT 1.
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TUSB3410 Bootcode Flow Setup Stage Status Stage Setup (0) IN(1) INT 1.Hardware generates interrupt to MCU. 2.Hardware sets NAK on both the IN and the OUT endpoints. 3.Set DIR bit in USBCTL to indicate the data direction. 4.Decode the setup packet. 5.If another setup packet arrives, abandon this one. 6.Execute appropriate routine per Table 11−10. 1.Hardware does NOT generates interrupt to MCU. Figure 11−2. Control Write Transfer Without Data Stage Table 11−10.
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TUSB3410 Bootcode Flow Table 11−11. Vector Interrupt Values and Sources 11.9.
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TUSB3410 Bootcode Flow 11.10 File Listings The TUSB3410 Bootcode Source Listing (SLLC139.zip) is available under the TUSB3410 product page on the TI website. Look under the Related Software link. The files listed below are included in the zip file. 78 • Types.h • USB.h • TUSB3410.h • Bootcode.h • Watchdog.h • Bootcode.c • Bootlsr.c • BootUSB.c • Header.h • Header.c • I2c.h • I2c.
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Electrical Specifications 12 Electrical Specifications 12.1 Absolute Maximum Ratings† Supply voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 3.6 V Input voltage, VI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VCC + 0.5 V Output voltage, VO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Electrical Specifications Electrical Characteristics (continued) TA = 25°C, VCC = 3.
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Application Notes 13 Application Notes 13.1 Crystal Selection The TUSB3410 requires a 12-MHz clock source to work properly. This clock source can be a crystal placed across the X1 and X2 terminals. A parallel resonant crystal is recommended. Most parallel resonant crystals are specified at a frequency with a load capacitance of 18 pF. This load can be realized by placing 33-pF capacitors from each end of the crystal to ground.
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Application Notes 13.3 Wakeup Timing (WAKEUP or RI/CP Transitions) The TUSB3410 can be brought out of the suspended state, or woken up, by a command from the host. The TUSB3410 also supports remote wakeup and can be awakened by either of two input signals. A low pulse on the WAKEUP terminal or a low-to-high transition on the RI/CP terminal wakes the device up. Note that for reliable operation, either condition must persist for approximately 3 ms minimum.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 27-Jul-2013 LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing TUSB3410IRHBR VQFN RHB 32 TUSB3410IRHBT VQFN RHB TUSB3410RHBR VQFN RHB TUSB3410RHBT VQFN RHB SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 32 250 180.0 12.4 5.3 5.3 1.5 8.0 12.0 Q2 32 3000 330.0 12.4 5.3 5.3 1.5 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 27-Jul-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TUSB3410IRHBR VQFN RHB 32 3000 338.1 338.1 20.6 TUSB3410IRHBT VQFN RHB 32 250 210.0 185.0 35.0 TUSB3410RHBR VQFN RHB 32 3000 338.1 338.1 20.6 TUSB3410RHBT VQFN RHB 32 250 210.0 185.0 35.
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MECHANICAL DATA MTQF002B – JANUARY 1995 – REVISED MAY 2000 VF (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,45 0,25 0,80 24 0,20 M 17 25 16 32 9 0,13 NOM 1 8 5,60 TYP 7,20 SQ 6,80 9,20 SQ 8,80 Gage Plane 0,05 MIN 0,25 0°– 7° 1,45 1,35 Seating Plane 0,75 0,45 0,10 1,60 MAX 4040172/D 04/00 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.