Data Manual April 2008 SLLS535E
Contents Contents Section 1 2 3 4 5 6 7 Page Controller Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 1.1 Acronyms and Terms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1−1 Main Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section 8 iv Page USB Function and Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1 8.1 USBCTL: USB Control Register (XDATA at F006) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1 8.1.1 USB Enumeration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−1 8.1.2 USB Reset . . . . . . . . . . . . . .
Contents Section Page 8.11 Serial Number Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−24 8.11.1 SERNUMn: Device Serial Number Register (Byte n, n = 0 to 5) (XDATA at F080 to F085) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8−24 9 Miscellaneous and GPIO Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Contents Section Page 11.5.10 TRANSBCNT3: USB or ATA/ATAPI Transfer Byte Count Register 3 (XDATA at F0D9) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11−14 11.5.11 CMNDLNGTH: Command Length Register (XDATA at F0DA) . . . . . . . . . . . . . . . . . . . 11−15 11.5.12 PIOSPAS: PIO Transfer Speed (Assertion Time) Register (XDATA at F0DC) . . . . . . 11−15 11.5.13 PIOSPRC: PIO Transfer Speed (Recovery Time) Register (XDATA at F0DD) . . . .
Contents Section 13.4 Page Compact Flash Storage Card Reader Application . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.1 Brief Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.2 Pin Assignment and Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13.4.3 Power-Up Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
List of Illustrations List of Illustrations Figure Title Page 3−1 TUSB6250 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−1 3−2 USB 20 PEI (Parallel Interface Engine) Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3−2 4−1 Controller 80-Pin TQFP Pin Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
Controller Description 1 Controller Description The TUSB6250 is a USB 2.0 HS-capable function controller with an integrated UTMI compliant PHY. The TUSB6250 is intended as a USB 2.0 to ATA/ATAPI bridge for storage devices using a standard ATA or ATAPI interface. The TUSB6250 is designed to use both the fast performance of the state machine and the programmability and flexibility of the embedded microcontroller and firmware.
Controller Description 1−2 TUSB6250 SLLS535E − April 2008
Main Features 2 Main Features 2.1 Universal Serial Bus (USB) 2.2 2.3 • Fully compliant with USB 2.0 specification: TID #40390418 • Integrated USB 2.
Main Features • − CD-R/W, DVD-R/W − Compact flash − PCMCIA type II card or hard drive − MO drive Dual-drive support − 2.4 2−2 Capable of supporting one master and one slave drive in any combination of ATA and ATAPI. • Provides easy control to put the ATA/ATAPI bus into a high-impedance state through one register bit setting.
Device Block Diagram 3 Device Block Diagram 24 MHz USB Host USB 2.0 UTMI USB 2.0 PIE (See Figure 3−2) UBM (USB Buffer Manager) 8K Byte (2K × 32) Data RAM 24K Byte (6K × 32) Configurable RAM for Code or Data 4K Byte (1K × 32) SPRAM 8K × 8 Code RAM 8K × 8 ROM 8051 (60 MHz) ATA/ATAPI Interface Controller Standard IDE Devices I2C Controller I2C EEPROM Figure 3−1.
Device Block Diagram Frame Timer UTMI-Compliant Phy Bus Monitor USB Reg. MCU Transaction Handler UBM (USB Buffer Manager) Figure 3−2. USB 2.
Device Parameter Information 4 Device Parameter Information 4.1 Pin Diagram SUSPEND P3.0/SIN P3.1/SOUT DVDD DVDD18 DGND P2.0 P3.2/CD1 P3.3/CD2 P3.4 P3.5 P2.1/PWR100 P2.2/PWR500 P2.3 DGND P2.4 P2.5 DVDD P2.
Device Parameter Information 4.2 Terminal Functions Table 4−1. Controller Terminal Description (80-Pin TQFP) TERMINAL NAME I/O NO. TYPE DESCRIPTION NOTES INTEGRATED USB 2.0 UTMI-COMPLIANT PHY AGND 7, 10, 16 GND Analog ground. All ground terminals should be connected together externally through a low-impedance path. All bypass capacitors to PLLVDD18, UDVDD18, and AVDD should connect to ground through a low-impedance path. AVDD 6, 13 PWR 3.3-V supply voltage for the integrated USB 2.
Device Parameter Information Table 4−1. Controller Terminal Description (80-Pin TQFP) (Continued) TERMINAL NAME I/O DESCRIPTION NO. TYPE NOTES XTAL2 17 O (12) 24-MHz crystal output. This terminal has a 1.8-V LVCMOS output buffer. XTAL1 18 I (11) 24-MHz crystal input. This terminal has a 1.8-V LVCMOS input buffer. CONTROLLER POWER/GROUND DGND 27,37,48, 56,66,75 GND Digital circuit ground terminals.
Device Parameter Information Table 4−1. Controller Terminal Description (80-Pin TQFP) (Continued) TERMINAL NAME I/O DESCRIPTION NO. TYPE NOTES P3.7 24 I/O (2)(5) (9) 5-V fail-safe general-purpose I/O with internal configurable pullup and pulldown resistors. This terminal can be used as a GPIO or DASP function, which is implemented by the end-product developer’s custom firmware. After a power-on reset, this terminal defaults as input with the internal pullup resistor enabled.
Device Parameter Information 4.3 Device Operation 4.3.1 Device Master Reset An external master reset signal, asynchronous to the TUSB6250 internal clock, is needed to reset the TUSB6250. This reset is referred to as the power-on reset throughout this document, which is connected to the RSTI terminal of the TUSB6250. Because the TUSB6250 has built-in noise debouncing circuitry, it also requires a valid clock signal present during the required active-low master reset window.
Device Parameter Information Depending on the type of firmware used as specified in the header block of the external I2C EEPROM, the boot code can determine: • Whether to perform connection to the USB host for enumeration before downloading the firmware into the internal code RAM • Whether to remain disconnected during the firmware code downloading process. In this case, the firmware, once in charge, assumes the responsibility of performing the connect and enumeration tasks.
Architecture Overview 5 Architecture Overview The overall functionality of the TUSB6250 is achieved by the combined interaction of major blocks or subcontrollers as shown earlier in Figure 3−1. These major blocks include the USB 2.0 UTMI-compliant PHY, USB 2.0 parallel interface engine (PIE), embedded microcontroller unit (MCU), USB buffer manager (UBM), ATA/ATAPI interface controller, and the I2C interface controller. 5.
Architecture Overview 5.2 Overview of Major Function Blocks 5.2.1 USB 2.0 UTMI-Compliant PHY The main functions of the integrated USB 2.0 UTMI-compliant PHY are to convert the received serial data stream from the USB host controller into parallel data packets that can be processed by the controller engine of the TUSB6250 and to perform parallel-to-serial conversion for the data packets to be transmitted to the USB host.
Architecture Overview The transaction handler manages the USB packet protocol requirement for the packets being received and transmitted on the USB by the TUSB6250. For the received packet, the transaction handler checks the packet identifier (PID) field to reveal the correct packet type from those defined by the USB 2.0 specification, such as token, data, handshake, and special packets.
Architecture Overview 5.2.6 I 2C Interface Controller The master-only I2C interface controller is responsible for acquiring the user-configurable descriptors and other configurable feature parameters from the external I2C EEPROM during initial power up. It is also used to download the application firmware from the external I2C EEPROM. The behavior of the I2C interface controller is controlled by the boot code (the microcode embedded in boot ROM) or application firmware. 5.3 Other Major Features 5.3.
Microcontroller Unit (MCU) 6 Microcontroller Unit (MCU) The embedded MCU is a high-performance version (8051 Warp core) of the standard 8-bit 8051 microcontroller, requiring just two clocks per machine cycle, while keeping functional compatibility with the standard part. This allows the embedded MCU to run up to six times faster than the standard part for the same power consumption.
Microcontroller Unit (MCU) addressable by the MCU and 8K bytes of RAM for the sector FIFO data space that is not directly accessible by the MCU. − The MCU can change this power-up RAM configuration by overwriting the value of the RAMPARTN bits.
Microcontroller Unit (MCU) 6.2 Internal XDATA Space [E000 → F0F9] The address range from E000 to F0F9 in XDATA space is reserved for data buffers and MMRs. • Data buffers of the EDB are all allocated in the address range E000 to EFFF, which are implemented by SPRAM. • MMRs can be allocated in the address range F000 to FFFF, which are implemented by registers.
Microcontroller Unit (MCU) Table 6−2.
Microcontroller Unit (MCU) Table 6−2.
Microcontroller Unit (MCU) Table 6−2.
Microcontroller Unit (MCU) Table 6−2.
Microcontroller Unit (MCU) 6.3 MCU Control and Status Registers (in SFR and ESFR Space) This section describes the PCON register (in standard 8051 SFR space) and all the registers added to the standard 8051 special function registers (SFRs) space in the TUSB6250 controller. These added registers are referred to as extended special function registers (ESFRs). For information regarding the standard SFRs, see the industry-standard 8051 specification.
Microcontroller Unit (MCU) Table 6−3.
Microcontroller Unit (MCU) 7 6 5 4 3 2 1 0 T7 T6 T5 T4 T3 T2 T1 T0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET 7−0 T [7:0] 00h FUNCTION RTK timer value. The RTKTM register defines the RTK (INT6) interrupt intervals in 10 µs increments. Note that a INT6 interrupt is generated only when T[7:0]>00 and EI6 is set (E16=1) in the IE1: interrupt enable register (SFR at E8). 00h = RTK timer is disabled.
Microcontroller Unit (MCU) For some removable media reader applications, if the media connector has connector detection pins at two opposite sides of the connector (for example, card reader application for compact flash card or PCMCIA type II card/drive), both CD1STEN and CD2STEN must be enabled to ensure correct detection of media insertion. The MCUCNFG register is cleared by a power-up reset or a WDT reset. A USB reset cannot reset the MCUCNFG register.
Microcontroller Unit (MCU) 7 6 5 4 3 2 1 0 RSV RSV RSV RSV R/O R/O R/O BANKSEL1 R/W BANKSEL0 R/W SCRATCH R/O BANKSEL2 R/W R/W BIT NAME RESET FUNCTION 0 SCRATCH 0 This is a scratch bit that can be read and written by the MCU for any end-product-specific function, if supported by the end-product custom firmware.
Interrupts 7 Interrupts 7.1 8051 Interrupt and Status Registers Most 8051 standard interrupt sources (except external interrupt-0 and external interrupt-1) are supported. In addition, interrupt-5 and interrupt-6 are provided. The real-time kernel (RTK) uses interrupt-6. All additional internal interrupt sources specified in Section 7.2, Additional Interrupt Sources, are ORed together to generate interrupt-5. The standard interrupt enable (IE) register controls the enabling of the interrupt source.
Interrupts 7.1.1 IE: Interrupt Enable Register (SFR at A8) 7 6 5 4 3 2 1 0 EA RSV EI5 ES ET1 RSV ETO RSV R/W R/O R/W R/W R/W R/O R/W R/O BIT NAME RESET 0 RSV 0 Reserved 1 ET0 0 Enable or disable timer-0 interrupt. ET0 = 0 Timer-0 interrupt is disabled ET0 = 1 Timer-0 interrupt is enabled 2 RSV 0 Reserved 3 ET1 0 Enable or disable timer-1 interrupt.
Interrupts 7.1.3 IE1: Interrupt Enable Register (SFR at E8) 7 6 5 4 3 2 1 0 RSV RSV RSV RSV RSV RSV RSV EI6 R/O R/O R/O R/O R/O R/O R/O R/W BIT NAME RESET 0 EI6 0 Enable or disable RTK interrupt. EI6 = 0 RTK interrupt is disabled EI6 = 1 RTK interrupt is enabled 7−1 RSV 0 Reserved FUNCTION 7.1.
Interrupts 7.2 Additional Interrupt Sources All nonstandard 8051 interrupts (USB, I2C, ATA/ATAPI etc.) are ORed to generate an internal INT5. INT5 is an active low-level interrupt (not edge triggered). A vector interrupt register is provided to identify all interrupt sources (see Section 7.2.1, VECINT: Vector Interrupt Register (ESFR at F7), for more details). Up to 64 interrupt vectors are provided. It is the responsibility of the MCU to read the vector and dispatch the proper interrupt routine.
Interrupts Table 7−2.
Interrupts 7−6 TUSB6250 SLLS535E − April 2008
8 USB Function and Registers The MCU and firmware or boot code configure the USB function characteristics of the TUSB6250 by configuring and updating the memory-mapped registers (located in XDATA space) described in this chapter. 8.1 USBCTL: USB Control Register (XDATA at F006) The USBCTL register is cleared by a power up or a WDT reset. A USB reset cannot reset the USBCTL register.
The following are some important notes regarding the USBCTL register. • The contents of this register are not affected by the USB reset. • The signaling connect/disconnect is totally controlled by the boot code or firmware by setting/clearing the CONT bit of this register. The TUSB6250 hardware does not perform any automatic action for this function. 8.1.2 USB Reset The TUSB6250 can detect a USB reset condition.
8.2 USBMSK: USB Interrupt Mask Register (XDATA at F007) Bits[5:0] of the USBMSK register provide a mechanism to allow the MCU and firmware to enable or disable the generation of certain types of interrupts based on the corresponding status or events that occurred. The USBMSK register is cleared by a power up or a WDT reset. A USB reset cannot reset the USBMSK register.
8.3 USBSTA: USB Status Register (XDATA at F008) Each bit in the USBSTA register can generate an interrupt if its corresponding mask bit is set in the USBMSK register. The related interrupt is cleared when the corresponding status bit is cleared by the MCU except the WAKCLK interrupt. All bits in this register are set by the hardware and can only be cleared by the MCU by writing a 1 to the proper bit location (writing a 0 has no effect).
For the TUSB6250, the timing to enter the USB suspend is controlled by the application firmware running on the embedded MCU. This flexibility allows the firmware to delay the time to go into suspend when the MCU is currently busy on some tasks that must be finished before the suspend. Because the firmware controls the time to enter the suspend, in order to be compliant with USB 2.0 specification, it is firmware responsibility to ensure that it clears the SUSPR interrupt status bit before 10 ms expires.
8.3.2.2 − The firmware then performs a read to the USBWKUP register to reveal which status-change event bit is set. If multiple events occurred, the firmware must service all of them individually. − After servicing the WAKCLK interrupt for each individual status-change event, the firmware must write a 1 to the corresponding bit in the USBWKUP register to clear such status-change event.
WAKCLK_en D Q WAKCLK Bit in USBSTA VBUSCHG_det CDCHG_det P34CHG_det ENZ P35CHG_det Q Write 1 to Clear the WAKCLK Bit) D Q P35CHG Bit in USBWKUP ENZ Q Write 1 to Clear the P35CHG Bit) D Q P34CHG Bit in USBWKUP ENZ Q Write 1 to Clear the P34CHG Bit) 60-MHz Core CLK D Q CDCHG Bit in USBWKUP ENZ Q Write 1 to Clear the CDCHG Bit) D Q VBUSCHG Bit in USBWKUP ENZ Write_1 to Clear the VBUSCHG Bit) Q Figure 8−1.
8.3.2.4 Register Settings Affect the WAKCLK Interrupt The seven enable bits listed in Table 8−1 greatly affect the behavior and function of the WAKCLK interrupt function. Table 8−1. Register Setting for the WAKCLK Interrupt and Remote Wakeup BIT NAME BIT LOCATION IN REGISTER FUNCTION CONTROLLED LPEN USBCTL[6] Low-power enable. LPEN controls whether the core clock of the TUSB6250 is shut down when the TUSB6250 enters the USB suspend state. WAKCLK USBMSK[2] WAKCLK interrupt enable.
8.4 FUNADR: Function Address Register (XDATA at F009) The FUNADR register contains the current setting of the USB device address assigned to the USB function of the TUSB6250 by the USB host. After a power-up reset or a USB reset, the default function address is 00h. During the enumeration of the USB function of the TUSB6250 by the host, the MCU and firmware load the assigned address from the host to the FA[6:0] bits of the FUNADR register on receiving a USB Set_Address request at the control endpoint.
8.6 USBFCL: USB Frame Counter Low-Byte Register (XDATA at F00B) The USBFCL register contains the read-only USB frame counter low-byte value of the 11-bit frame number value received from the USB host in the start-of-frame packet. The frame number bit values are updated by the hardware for each USB frame with the frame number field value received in the USB start-of-frame packet. The frame number can be used as a time stamp by the USB function.
events do not trigger a new WAKCLK interrupt if there is already a WAKCLK interrupt in the queue. This avoids the MCU being interrupted by too many WAKCLK interrupts. • Following the same guideline, when consecutive status-change events happen: − If the source of the new status-change event that occurred is different from the ones that already occurred, the new status-change event is logged in the corresponding status-change bit of the USBWKUP register.
8.9 BIT NAME RESET FUNCTION 2 P34ST 0 P3.4 status bit. This bit represents the debounced status value on the P3.4 pin. 3 P35ST 0 P3.5 status bit. This bit represents the debounced status value on the P3.5 pin. 4 CDCHG 0 Compact flash card/media detection pin status-change bit. This bit, when set, indicates a status change occurred at either the CD1 or CD2 pin. The firmware must read the status of these two pins to ensure a correct media insertion.
8.9.1 IEPCNFG_0: Input Endpoint-0 Configuration Register (XDATA at F000) The IEPCNFG_0 register contains various bits used to configure and control this endpoint. 7 6 5 4 3 2 1 0 UBME NAK_INTE TOGLE RSV STALL USBIE R/W R/W R/O R/O R/W R/W BZ1 R/W BZ0 R/W BIT NAME RESET FUNCTION 1−0 BZ[1:0] 00b Endpoint-0 buffer size for IN and OUT transaction. The value of this field also defines the starting address of the input buffer. See Table 8−3.
8.9.3 OEPCNFG_0: Output Endpoint-0 Configuration Register (XDATA at F003) The OEPCNFG_0 register contains various bits used to configure and control this endpoint. 7 6 5 4 3 2 1 0 UBME NAK_INTE TOGLE RSV STALL USBIE RSV RSV R/W R/W R/O R/O R/W R/W R/O R/O BIT NAME RESET FUNCTION 1−0 RSV 00 Reserved = 00 2 USBIE 0 USB interrupt enable on transaction completion. Set/cleared by the MCU.
Table 8−4 shows the buffer location address map for a single buffer with a buffer size of 64 bytes. Table 8−4. EDB0 Buffer Locations (in SPRAM) ADDRESS NAME EFFF TOPBUFF DESCRIPTION Top of buffer space ↑ | | | | | Buffer space 4K – 128 bytes free ↓ E080 ↑ E07F ↑ | ↓ I Input endpoint_0, buffer I 64 bytes E040 ↓ E03F ↑ I Output endpoint_0, buffer | ↓ ↑ | ↓ 64 bytes E000 NOTE: This table is based on a single buffer with a buffer size of 64 bytes for both input and output endpoint-0. 8.
Endpoint # OUT Bit Value 1 1 1 1 0 0 0 0 0 E2 E1 E0 1 0 0 0 Bit Number A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 Figure 8−3. OUT-Endpoint Index Generation Table 8−5.
8.10.1 IEPCNFG_n: Input Endpoint Configuration Register (n = 1 to 4) (XDATA at F010, F020, F030, F040) The IEPCNFG register contains various bits used to configure and control the specified endpoint. 8.10.2 7 6 5 4 3 2 1 0 UBME NAK_INTE TOGLE DBUF STALL USBIE RST_TOGLE MAP_SECF R/W R/W R/O R/W R/W R/W W/O R/W BIT NAME RESET 0 MAP_SECF 0 Map data buffer to sector FIFO RAM. MAP_SECF = 0 Endpoint data is stored in 4K-byte endpoint data buffer.
8.10.3 IEPBCNLX_n: Input Endpoint X-Buffer Byte-Count Low-Byte Register (n = 1 to 4) (XDATA at F012, F022, F032, F042) The IEPBCNLX_n register contains the lower 8-bit value in the X-buffer that is used to specify the amount of data to be transmitted in a data packet to the USB host. 8.10.
5. Once the USB host acknowledges the host-IN transfer with an ACK, the TUSB6250 hardware sets the NAK bit to 1, so that any new host-IN request is NAKed until the MCU and firmware get the new required data payload ready. 8.10.5 IEPSIZXY_n: Input Endpoint X/Y-Buffer Size Register (n = 1 to 4) (XDATA at F014, F024, F034, F044) The IEPSIZXY register contains the X- and Y-buffer size for the specified input endpoint. 7 8.10.
8.10.8 IEPBCNHY_n: Input Endpoint Y-Buffer Byte-Count High-Byte Register (n = 1 to 4) (XDATA at F017, F027, F037, F047) The IEPBCNHY_n register contains the NAK bit and the higher 3-bit value in the Y-buffer that is used to specify the amount of data to be transmitted in a data packet to the USB host. See the procedure described in the IEPBCNHX_n register when using the NAK bit for flow control handshake. 8.10.
8.10.10 OEPBBAX_n: Output Endpoint X-Buffer Base Address Register (n = 1 to 4) (XDATA at F019, F029, F039, F049) The OEPBBAX_n register contains the X-buffer base address for the specified output endpoint. 7 6 5 4 3 2 1 0 A11 A10 A9 A8 A7 A6 A5 A4 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 A[11:4] 00h This is the middle 8-bit value of the complete (1110 and A[11:4] and 0000) 16-bit X-buffer base address. See Figure 8−4. This value is set by the MCU.
• The UBM (USB buffer manager, a DMA engine on the USB side) of the TUSB6250 loads the data into either the X-buffer or Y-buffer, depending on the following conditions: − If DBUF = 1, TOGLE = 0, and the data PID = DATA0: The UBM loads the data into the X-buffer of the out-endpoint data buffer (4K-byte EDB) and updates the X-buffer byte-count information in the OEPBCNLX_n and OEPBCNHX_n registers.
8.10.16 OEPBCNHY_n: Output Endpoint Y-Buffer Byte-Count High-Byte Register (n = 1 to 4) (XDATA at F01F, F02F, F03F, F04F) The OEPBCNHY_n register contains the NAK bit and the higher 3-bit value in the Y-buffer that is used to specify the amount of data received in a data packet from the USB host. See the procedure described in the OEPBCNHX_n register when using the NAK bit for flow control handshake.
8.11.1 SERNUMn: Device Serial Number Register (Byte n, n = 0 to 5) (XDATA at F080 to F085) After a power-up reset, the SERNUMn read-only register (SERNUMn) contains byte n of the complete 48-bit device serial number from the on-chip serial die ID number. A USB reset cannot reset the SERNUMn register.
Miscellaneous and GPIO Configuration Registers 9 Miscellaneous and GPIO Configuration Registers The TUSB6250 offers up to 13 GPIOs and three additional general-purpose open-drain outputs that can be used for an end-product-specific function. All the GPIOs and general-purpose open-drain outputs are mapped to port 2 and port 3 of the embedded MCU. Table 9−1 illustrates the TUSB6250 GPIO port mapping for the embedded MCU and some recommended usage. Table 9−1.
Miscellaneous and GPIO Configuration Registers • 9.1 Following the standard 8051 convention, both port 2 and port 3 are bit addressable, which implies that within the same GPIO port, some pins can be configured as inputs and others as outputs. MODECNFG: Mode Configuration Register (XDATA at F088) The MODECNFG register contains several parameters the MCU can use to configure the code and data RAM partition, polarity of the INTRQ pin, and code RAM write access enable.
Miscellaneous and GPIO Configuration Registers 9.2 PUPDSLCT_P2: GPIO Pullup and Pulldown Resistor Selection Register for Port 2 (XDATA at F08A) The PUPDSLCT_P2 register allows the MCU to select either the pullup or pulldown resistors on the MCU port-2 GPIO pins. To turn off both the pullup and pulldown resistors, the MCU must configure the corresponding bit in the PUPDPWDN_P2 register. PUSEL[N] means the pullup/pulldown resistor selection for pin P2.N.
Miscellaneous and GPIO Configuration Registers 9.3 PUPDWDN_P2: GPIO Pullup and Pulldown Resistor Power-Down Register for Port 2 (XDATA at F08B) The PUPDWDN_P2 register allows the MCU to enable/disable both the internal pullup/pulldown resistors connected to port 2 GPIO pins. To choose the desired pullup or pulldown resistor for a particular pin, the MCU must ensure the correct setup is done in the PUPDSLCT_P2 register before enabling the corresponding bit in the PUPDWDN_2 register.
Miscellaneous and GPIO Configuration Registers 9.5 PUPDPWDN_P3: GPIO Pullup and Pulldown Resistor Power-Down Register for Port 3 (XDATA at F08D) The PUPDWDN_P3 register allows the MCU to enable/disable the internal pullup and pulldown resistors that are connected to the port-3 GPIO pins. To choose the desired pullup or pulldown resistor for a particular pin, the MCU must ensure that the correct setup is done in the PUPDSLCT_P3 register before enabling the corresponding bit in this register.
Miscellaneous and GPIO Configuration Registers 9.6 PUPDFUNC: Pullup/Pulldown Configuration Register for Functional Pins (XDATA at F08E) The PUPDFUNC register allows the MCU to select/deselect and enable/disable the internal pullup or pulldown resistor connection on certain functional pins.
Miscellaneous and GPIO Configuration Registers 9.7 PUPDSLCT_ATPOUT: Pullup and Pulldown Resistor Selection Register for ATA/ATAPI Outputs (XDATA at F08F) The PUPDSLCT_ATPOUT register allows the MCU to select the desired integrated pullup or pulldown resistors for the TUSB6250 ATA/ATAPI output terminals. Normally, these resistors are not used in functional operation. However, they can be used to help achieve the low-power suspend budget for bus-powered applications.
Miscellaneous and GPIO Configuration Registers 9.8 PUPDPWDN_ATPOUT: Pullup and Pulldown Resistors Power-Down Register for ATA/ATAPI Outputs (XDATA at F090) The PUPDPWDN_ATPOUT register allows the MCU to enable/disable all of the pullup and pulldown resistors for the TUSB6250 ATA/ATAPI output terminals. To select the desired pullup or pulldown resistor, the MCU must configure the appropriate register bit in PUPDSLCT_ATPOUT.
I 2C Interface Controller 10 I2C Interface Controller The master-only I2C interface controller in the TUSB6250 provides a simple two-wire serial interface for the MCU to communicate with the external EEPROM. It supports single-byte or multiple-byte read and write operations. The I2C interface controller can be programmed to operate at either 100 Kbit/sec or 400 Kbit/sec. In addition, the protocol supports 8-bit or 16-bit addressing for accessing the I2C slave device memory locations.
I 2C Interface Controller 10.1 I2C Registers IECSCR: I 2C Status and Control Register (XDATA at F0B0) 10.1.1 The IECSCR register contains the I2C EERPOM speed, error condition indication, and provides status information for the I2C data registers. It is also used to control the stop condition for read and write operation. In addition, it provides transmitter and receiver handshake signals.
I 2C Interface Controller 10.1.3 I2CDIN: I 2C Data_In Register (XDATA at F0B2) The I2CDIN register holds the received data returned by read operation to the external I2C EEPROM. 7 6 5 4 3 2 1 0 D7 D6 D5 D4 D3 D2 D1 D0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME 7−0 10.1.
I 2C Interface Controller 10.2 Random-Read Operation A random read requires a dummy byte-write sequence to load in the data word address. Once the device-address word and the data-word address are clocked out and acknowledged by the device, the MCU starts a current-address sequence. The following describes the sequence of events to accomplish this transaction. Device Address + EEPROM [High Byte] • The TUSB6250 hardware detects 3-ms bus idle. • The MCU sets I2CSCR [STOP] = 0.
I 2C Interface Controller 10.4 Sequential-Read Operation Once the I2C EEPROM address is set, the MCU can execute a sequential-read operation by executing the following steps (this example illustrates a 32-byte sequential read): Device Address • The MCU sets I2CSCR [STOP] = 0. This forces the I2C controller to not generate a stop condition after the I2CDIN register contents are received. • The MCU writes the device address (R/W bit = 1) to the I2CADR register (read operation).
I 2C Interface Controller 10.5 Byte-Write Operation The byte-write operation involves three phases: device address + EEPROM [high byte] phase, EEPROM [low byte] phase, and EEPROM [DATA] phase. The following describes the sequence of events to accomplish the byte-write transaction. Device Address + EEPROM [High Byte] • The MCU sets I2CSCR [STOP] = 0. This forces the I2C interface controller not to generate a stop condition after the contents of the I2CDOUT register are transmitted.
I 2C Interface Controller 10.6 Page-Write Operation The page-write operation is initiated in the same way as the byte-write operation, with the exception that a stop condition is not generated after the first I2C EEPROM [DATA] is transmitted. The following describes the sequence of writing 32 bytes in page mode. Device Address + EEPROM [High Byte] • The MCU sets I2CSCR [STOP] = 0.
I 2C Interface Controller 10.7 I2C EEPROM Head Block To fully use the maximum speed of the variety of I2C EEPROMs on the market, the I2C interface controller in the TUSB6250, along with boot code and firmware, features a special mechanism to detect the speed supported by the I2C EEPROM connected to its I2C port.
ATA/ATAPI Interface Port 11 ATA/ATAPI Interface Port The ATA/ATAPI controller embedded in the TUSB6250 acts as a bridge between the device USB interface and ATA/ATAPI interface. A high-performance DMA engine is implemented in the ATA/ATAPI controller to move data automatically between the TUSB6250 sector FIFO and the ATA/ATAPI interface port where the external ATA/ATAPI mass storage device is connected. Unlike other state-machine-based USB 2.
ATA/ATAPI Interface Port 11.1 TUSB6250 ATA Controller Architecture Overview The TUSB6250 ATA/ATAPI controller contains three state machines, the ATA/ATAPI CSR registers, and the sector FIFO controller, as illustrated in Figure 11−2. The sector FIFO controller is the high-performance DMA engine discussed in the previous section.
ATA/ATAPI Interface Port The sector FIFO can be accessed by the UBM, ATA/ATAPI controller, and the MCU, where the MCU can only be indirectly accessed by going through the ATA/ATAPI CSR and the sector FIFO controller. The UBM access has the highest priority, the ATA/ATAPI controller has the middle level access priority, and the MCU access has the lowest priority. 11.1.
ATA/ATAPI Interface Port 11.2 ATA/ATAPI Port Power-On Sequencing and 3-State Control As described in Section 5.3.1, Unique Power-On Sequencing to the Storage Device, the TUSB6250 offers unique power-on sequencing features, which provides design flexibility to the drive developers, especially if multiple devices share the ATA/ATAPI bus.
ATA/ATAPI Interface Port Pulled High by External Pullup Resistor Signal-Connect to the USB Host PWR100 TUSB6250 Configured by the USB Host PWR500 Pulled Low by Internal Pulldown Resistor Driven Low by TUSB6250 Under Firmware Control RST_ATA t0 Figure 11−3. ATA/ATAPI Bus Power-Up and Reset Sequence Note that the PWR500 function showed in the Figure 11−3 is not implemented in the TUSB6250 hardware.
ATA/ATAPI Interface Port 11.3 TUSB6250 ATA/ATAPI Controller Transfer Modes The supported Universal Serial Bus Mass Storage Class Bulk-Only Transport protocol uses only the bulk endpoint for the transport of command, data, and status. The transport command set used in the bulk-only protocol is actually based on the SCSI transparent command set, which is wrapped with some information related to the bulk-only protocol, to form the command block wrapper (CBW) for a specific transport.
ATA/ATAPI Interface Port • Semiautomatic mode—In this mode, similar to the fully manual mode, the MCU is also responsible for handling all data movement between the 4K-byte EDB and the ATA/ATAPI interface for the command and status stages.
ATA/ATAPI Interface Port 11.4 ATA/ATAPI Group 0 (Task_File) Registers Table 11−1.
ATA/ATAPI Interface Port • If the AUTO_CMD bit is not set (implies the fully-auto mode is not used): The Task_File0 to Task_File15 registers are not used by the transaction state machine of the ATA/ATAPI controller. The MCU is responsible to write command block registers manually to set up the command, read the status register to check if the device is busy or any error condition has occurred, and transfer command packets if the device is an ATAPI device.
ATA/ATAPI Interface Port 7 6 5 4 3 2 1 0 UABYCNAB RSV RSV RSV USBWPNABRTEN DMADIRCKEN TRANS_MOD1 TRANS_MOD0 R/O R/O R/O R/W R/W R/W R/W R/W BIT NAME RESET 1−0 TRANS_MOD[1:0] 00 ATA/ATAPI transfer mode. TRANS_MOD = 00 PIO mode TRANS_MOD = 01 Multiword DMA mode TRANS_MOD = 10 Reserved TRANS_MOD = 11 Ultra DMA mode 2 DMADIRCKEN 0 DMA direction check enable.
ATA/ATAPI Interface Port 11.5.2 ATPIFCNFG1: ATA/ATAPI Interface Configuration Register 1 (XDATA at F0D1) 7 6 5 4 3 2 1 0 ATP_MOD SOFT_RST HARD_RST XFER_DIR AUTO_CMD START_ATAPI NON_DA_CMD DEV_SEL R/W W/C R/W R/W R/W W/C R/W R/W BIT NAME RESET FUNCTION 0 DEV_SEL 0 ATAPI device select. When ATP_MOD = 1 and AUTO_CMD =1 and START_ATAPI =1 and: DEV_SEL = 0 The internal state machine sets the DEV bit of the device/head register to 0 when it sends the packet command.
ATA/ATAPI Interface Port 11.5.3 ATPACSREG0: ATA/ATAPI Access Register 0 (XDATA at F0D2) ATPACSREG1 and ATPACSREG0 are the ATA/ATAPI register access holding registers. For register write transfer, this register set contains the data to be written to a register. For register read transfer, after the ATA/ATAPI register read transfer is done, ATP_DATA[15:0] contains the read value. • If the read transfer does not access the data register, only ATP_DATA[7:0] contains valid data.
ATA/ATAPI Interface Port Table 11−3 shows the register address map for the command and control block registers used in the ATA and ATAPI devices. Table 11−3.
ATA/ATAPI Interface Port The complete 32-bit transfer byte count (TRNS_BCN[31:0]) is stored in the USB or the ATA/ATAPI transfer byte-count registers 0−3. The initial TRNS_BCN[31:0] is used to indicate the expected total transfer byte count for a command, which is equal to the dCBWDataTransferLength defined by the Universal Serial Bus Mass Storage Class Bulk-Only specification. After data is transferred through the USB or ATA/ATAPI interface, TRNS_BCN[31:0] is decremented accordingly.
ATA/ATAPI Interface Port 11.5.11 CMNDLNGTH: Command Length Register (XDATA at F0DA) 7 6 5 4 3 2 1 0 RSV ATP_TRANS_DONE ATP_DIS CMD_LENG4 CMD_LENG3 CMD_LENG2 CMD_LENG1 CMD_LENG0 R/O R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 4−0 CMD_LENG[4:0] 00h Command length[4:0]. These bits are only used by the ATAPI device during the fully automatic mode, when the AUTO_CMD bit is set in the ATPIFCNFG1 register.
ATA/ATAPI Interface Port 11.5.13 PIOSPRC: PIO Transfer Speed (Recovery Time) Register (XDATA at F0DD) The PIOSPRC register contains PIO transfer speed (recovery time) along with write data hold time information. The PIOSPRC register is cleared by a power-up or a WDT reset. A USB reset cannot reset the PIOSPRC register. The unit of recovery time is defined as a single cycle of a 60-MHz clock (16.
ATA/ATAPI Interface Port The unit of recovery time is defined as a single cycle of a 60-MHz clock (16.67 ns), which reflects the tK parameter (for multiword DMA) or tRP parameter (for ultra DMA) value in an actual ATA/ATAPI drive (see the ATA/ATAPI-5 specification, pages 294 and 300).
ATA/ATAPI Interface Port Table 11−5. Multiword DMA Mode and Timing Correlation Chart CYCLE TIME (t0) MWDMA TRANSFER MODE ASSERTION TIME (tD) TIME (ns) TIME (ns) RECOVERY TIME (tK) # OF CLKS (SEE NOTE 1) TIME (ns) # OF CLKS (SEE NOTE 1) SPEC (MIN) ACTUAL SPEC (MIN) ACTUAL REGISTER SETTING ACTUAL SPEC (MIN) ACTUAL REGISTER SETTING ACTUAL 0 480 483.43 215 216.71 12 13 250 266.72 14 16 1 150 150.03 80 83.35 4 5 50 66.68 2 4 2 120 133.36 70 83.35 4 5 25 50.
ATA/ATAPI Interface Port 11.6 ATA/ATAPI Group 2 Registers Table 11−7.
ATA/ATAPI Interface Port MACS_BUSY to 1. When the internal logic reads from the sector FIFO memory, it loads the 32-bit data into the MCU data Byte_3 register (MCUBYTE3), MCU data Byte_2 register (MCUBYTE2), MCU data Byte_1 register (MCUBYTE1), MCU data Byte_0 register (MCUBYTE0), clears MACS_BUSY to 0, and increments MACS_ADR[12:0] by 1. 3.
ATA/ATAPI Interface Port 11.6.5 11.6.6 11.6.7 MCUACSL: MCU Access Address Low-Byte Register (XDATA at F0E4) 7 6 5 4 3 2 1 0 MACS_ADR7 MACS_ADR6 MACS_ADR5 MACS_ADR4 MACS_ADR3 MACS_ADR2 MACS_ADR1 MACS_ADR0 R/W R/W R/W R/W R/W R/W R/W R/W BIT NAME RESET FUNCTION 7−0 MACS_ADR[7:0] 00h MCU access address[7:0]. These bits contain the MCU access sector FIFO memory address lower 8 bits.
ATA/ATAPI Interface Port 2 ATP_BYTECN_MIS 0 ATA/ATAPI byte-count mismatch. This bit, when set, indicates that there is a byte-count mismatch that occurred for the current data transfer at the ATA/ATAPI interface. The MCU is responsible for reading the ATA/ATAPI interface status register or transfer byte-count register to determine the actual event causing the mismatch. 3 USB_XFR_DN 0 USB transfer done.
ATA/ATAPI Interface Port 3 ATP_BSY 0 ATA/ATAPI busy. This bit, when set, indicates the ATA/ATAPI device is busy at the start of the command (after writing START_ATAPI). The command is not executed in the autocommand mode. The MCU must read the Task_File registers to determine why the ATA/ATAPI device is busy. 7−4 RSV 0h Reserved 11.6.9 ATPSTATUS: ATA/ATAPI Interface Status Register (XDATA at F0EA) The ATPSTATUS register provides some status information on the ATA/ATAPI interface.
ATA/ATAPI Interface Port BIT NAME RESET 4 BUFOVFLOW 0 FUNCTION Internal buffer overflow error. The internal buffer refers to the 6-byte internal buffer space outside of sector FIFO designed to handle extra data that may be received from the ATA/ATAPI device in pausing a UDMA read operation.
ATA/ATAPI Interface Port 11.6.11 SECWRPTH: Sector FIFO Write Pointer High-Byte Register (XDATA at F0EC) 7 6 5 4 3 2 1 0 SEC_FIFO_EMPT RSV WR_PTR13 WR_PTR12 WR_PTR11 WR_PTR10 WR_PTR9 WR_PTR8 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 5−0 WR_PTR[13:8] 000000 These bits contain the sector FIFO write pointer higher 6-bit value. Read-only WR_PTR[13:0] is used as the current write pointer to write data into sector FIFO.
ATA/ATAPI Interface Port 11.6.15 SECRDPTH: Sector FIFO Read Pointer High-Byte Register (XDATA at F0F0) 7 6 5 4 3 2 1 0 RSV RSV RD_PTR13 RD_PTR12 RD_PTR11 RD_PTR10 RD_PTR9 RD_PTR8 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET FUNCTION 5−0 RD_PTR[13:8] 000000 These bits contain the sector FIFO read pointer higher 6-bit value. Read-only The sector FIFO controller uses RD_PTR[13:0] as the current read pointer to read data out from sector FIFO.
ATA/ATAPI Interface Port 11.6.18 ULRCVEXCNT: Ultra Receive Extra Word Count Register (XDATA at F0F9) 7 6 5 4 3 2 1 0 RSV RSV RSV RSV WORDCN3 WORDCN2 WORDCN1 WORDCN0 R/O R/O R/O R/O R/O R/O R/O R/O BIT NAME RESET 3−0 WORDCN[3:0] 0h FUNCTION Ultra receive extra word count. The value in this register indicates the word count of the extra number of words received between the TUSB6250 pausing and terminating a UDMA read transfer after the expected byte count is received.
ATA/ATAPI Interface Port 11−28 TUSB6250 SLLS535E − March 2008
Electrical Specifications 12 Electrical Specifications 12.1 Absolute Maximum Ratings† Supply voltage, VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4 V Input voltage, VI, 3.3-V LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to VDD + 0.5 V 5-V failsafe TTL-compatible LVCMOS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
Electrical Specifications 12.3 Electrical Characteristics for the Controller Digital Core, TA = 25°C, VDD = 3.
Electrical Specifications 12.6 Electrical Characteristics for the Integrated USB 2.0 Transceiver, TA = 25°C, VDDA = 3.3 V ±5%, VSS = 0 V (unless otherwise noted)† PARAMETER MIN TYP MAX UNIT INPUT LEVELS FOR FULL SPEED VID VCM High-speed differential input threshold 0.2 V Differential common mode range 0.8 2.
Electrical Specifications 12−4 TUSB6250 SLLS535E − April 2008
Application Information 13 Application Information 13.1 Crystal Selection and Reference Circuitry The TUSB6250 is designed to use an external 24-MHz crystal connected between the XTAL1 and XTAL2 pins to provide the reference for an internal oscillator circuit. The oscillator, in turn, drives a PLL circuit that generates the various clocks required for transmission and resynchronization of data at the full-speed and high-speed data rates.
Application Information 13.2 Reset Timing Reference There are two requirements for the reset signal timing. • The minimum reset pulse width is 100 µs at power up. This time is measured from the time the power ramps up to 90% of the nominal VDD, until the reset signal is no longer active (reset is active as long as it is less than 1.2 V). • The clock must be valid during the last 60 µs of the reset window. The clock is valid when the oscillation on the XTAL2 pin exceeds 1.2 Vp-p.
Application Information 13.4 General ATA/ATAPI Device Application Information 13.4.1 ATA/ATAPI Connector Pin Diagram Table 13−1 shows all the signals on the standard 40-pin ATA/ATAPI connector defined by the ATA/ATAPI-5 specification. Table 13−1.
Application Information The IOCS16 signal was defined as IOCS16 in ATA-2, ANSI X3.279-1996, and has been obsolete since ATA-3 was released. IOCS16 is an output from the device to indicate whether the device expects an 8-bit or 16-bit data transfer. Because most ATA/ATAPI devices support a 16-bit data transfer, there is no need to support the IOCS16 pin function. 13.4.2.
Application Information 13.4.3 Special Note About Pullup and Pulldown Resistors for ATA/ATAPI Signals The TUSB6250 provides internal 200-µA pullup and/or pulldown resistors to most ATA/ATAPI bus signals, which can be used during power-on sequencing or active modes to avoid bus floating. To ensure compliance with the ATA/ATAPI specification, it is recommended to implement pullup and pulldown resistors at the board level with the value defined by the ATA/ATAPI-5 specification: 13.4.
Application Information 13.5 CompactFlashE Storage Card Reader Application 13.5.1 Brief Introduction CompactFlash storage cards provide a flash-memory-technology-independent interface to access the flash cards.
Application Information Table 13−3. CompactFlashE Card System Performance (Reference Only) PARAMETER CONDITION VALUE Sleep to write 2.5 ms maximum Sleep to read 2 ms maximum Reset to ready 50 ms typical, 400 ms maximum To/from host 16−20-MBps burst Command to DRQ 1.25 ms maximum Start-up times Active to sleep delay Programmable Data transfer rate Controller overhead 13.5.1.2 Capacity, Connector, Header, and Ejector • • • 13.5.
Application Information Table 13−4.
Application Information 10. Because the CompactFlash storage card permits 8-bit data transfer only if a user issues a set feature command to put the device in the 8-bit mode, there is no need to support it as long as the host driver prohibits such command. The IOCS16 pin at the CompactFlash storage card reader side of the connector should be left open. See Section 13.4.2.2, IOCS16, Pin 32 on the ATA/ATAPI Connector, for a detailed explanation. 11.
Application Information 13−10 TUSB6250 SLLS535E − April 2008
MECHANICAL DATA MTQF009A – OCTOBER 1994 – REVISED DECEMBER 1996 PFC (S-PQFP-G80) PLASTIC QUAD FLATPACK 0,27 0,17 0,50 60 0,08 M 41 61 40 80 21 1 0,13 NOM 20 Gage Plane 9,50 TYP 12,20 SQ 11,80 0,25 14,20 SQ 13,80 0,05 MIN 0°– 7° 0,75 0,45 1,05 0,95 Seating Plane 0,08 1,20 MAX 4073177 / B 11/96 NOTES: A. All linear dimensions are in millimeters. B. This drawing is subject to change without notice. C.
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