TUSB9260 USB 3.0 TO SATA BRIDGE Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com Contents 7 ................................................................................................................ 5 1.1 TUSB9260 Features ........................................................................................................ 5 1.2 Target Applications ......................................................................................................... 5 INTRODUCTION ............................................
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com List of Figures 2-1 Device Block Diagram ............................................................................................................. 7 5-1 Typical Crystal Connections ....................................................................................................
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com List of Tables 3-1 GPIO/PWM LED Designations ................................................................................................... 9 4-1 I/O Definitions ..................................................................................................................... 11 4-2 Clock and Reset Signals ........................................................................................................
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com USB 3.0 TO SATA BRIDGE Check for Samples: TUSB9260 1 MAIN FEATURES 1.1 TUSB9260 Features • Universal Serial Bus (USB) – SuperSpeed USB 3.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 2 INTRODUCTION 2.1 System Overview www.ti.com The TUSB9260 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com GRSTz ROM ARM Cortex M3 VDD3.3 VDD1.8 RAM Power and Reset Distribution TCK TMS TDO TDI TRST JTAG VDD1.1 Data Path RAM 80 kB XI Clock Generation XO USB 3.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 3 OPERATION 3.1 General Functionality www.ti.com The TUSB9260 ROM contains boot code that executes after a global reset which performs the initial con-figuration required to load a firmware image from an attached SPI flash memory to local RAM.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com 3.2 Firmware Support Default firmware support is provided for the following: • USB 3.0 SuperSpeed and USB 2.0 High-Speed and Full-Speed • USB Attached SCSI Protocol (UASP) • USB Mass Storage Class (MSC) Bulk-Only Transport (BOT) – Including the 13 Error Cases • USB Mass Storage Specification for Bootability • USB Device Class Definition for Human Interface Devices (HID) – Firmware Update and Custom Functionality (e.g.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 3.4 www.ti.com Power Up and Reset Sequence The TUSB9260 does not have specific power sequencing requirements with respect to the core power (VDD), I/O power (VDD33), or analog power (VDDA11, VDDA33, VDDA18, and VDDR18). The core power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not powered up if all of these constraints are met: • All maximum ratings and recommended operating conditions are observed.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com 4 SIGNAL DESCRIPTIONS Table 4-1. I/O Definitions I/O TYPE DESCRIPTION I Input O Output I/O Input - Output PU Internal pull-up resistor PD Internal pull-down resistor PWR Power signal Table 4-2. Clock and Reset Signals TERMINAL NAME PIN NO. I/O DESCRIPTION GRSTz 4 I PU Global power reset. This reset brings all of the TUSB9260 internal registers to their default states.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com Table 4-4. USB Interface Signals TERMINAL PIN NO.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com Table 4-6. JTAG, GPIO, and PWM Signals TERMINAL NAME PIN NO. I/O DESCRIPTION JTAG_TCK 25 I PD JTAG test clock JTAG_TDI 26 I PU JTAG test data in JTAG_TDO 27 O PD JTAG test data out JTAG_TMS 28 I PU JTAG test mode select JTAG_TRSTz 29 I PD JTAG test reset GPIO9/UART_TX 6 I/O PU GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com Table 4-7. Power and Ground Signals TERMINAL PIN NO. I/O VDDR18 48, 62 PWR 1.8-V power rail VDDA18 37 PWR 1.8-V analog power rail VDD 1, 12, 19, 32, 38, 41, 44, 47, 49, 55, 58, 61, 63, 64 PWR 1.1-V power rail VDD33 7, 24, 50, 51 PWR 3.3-V power rail VDDA33 34 PWR 3.3-V analog power rail VSSOSC 53 PWR Oscillator ground. If using a crystal, this should not be connected to PCB ground plane.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com 5 CLOCK CONNECTIONS 5.1 Clock Source Requirements The TUSB9260 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 5.3 www.ti.com Oscillator XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 40-MHz clock can be used. Table 5-1.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 www.ti.com 6 ELECTRICAL SPECIFICATIONS 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDDR18/ VDDA18 Steady-state supply voltage –0.3 to 2.45 V VDD Steady-state supply voltage –0.3 to 1.4 V VDD33/ VDDA33 Steady-state supply voltage –0.3 to 3.8 V 6.2 Recommended Operating Conditions over operating free-air temperature range (unless otherwise noted) MIN NOM MAX UNIT 1.
TUSB9260 SLLS962D – DECEMBER 2009 – REVISED MAY 2011 7 www.ti.com POWER CONSUMPTION All transfers are to a SATA Gen II SSD. A SATA Gen I target yields an approximate 10-mA power savings on the 1.1-V rail. Table 7-1. SuperSpeed USB Power Consumption POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL IDLE CURRENT (mA) (2) VDD11 (3) 319 308 VDD18 (4) 58 58 6 6 VDD33 (1) (2) (3) (4) (5) (5) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only.
PACKAGE OPTION ADDENDUM www.ti.com 8-Jan-2013 PACKAGING INFORMATION Orderable Device Status (1) TUSB9260PVP ACTIVE Package Type Package Pins Package Qty Drawing HTQFP PVP 64 250 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) CU NIPDAU MSL Peak Temp Samples (3) (Requires Login) Level-3-260C-168 HR (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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