TUSB9261 USB 3.0 TO SATA BRIDGE Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Contents 1 MAIN FEATURES 1.1 1.2 ................................................................................................................ 5 TUSB9261 Features ........................................................................................................ 5 Target Applications ......................................................................................................... 5 8 ........................................
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 List of Figures 3-1 Device Block Diagram ............................................................................................................. 8 6-1 Typical Crystal Connections ....................................................................................................
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com List of Tables 4-1 GPIO/PWM LED Designations ................................................................................................. 10 5-1 I/O Definitions ..................................................................................................................... 13 5-2 Clock and Reset Signals ........................................................................................................
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 USB 3.0 TO SATA BRIDGE Check for Samples: TUSB9261 1 MAIN FEATURES 1.1 TUSB9261 Features • Universal Serial Bus (USB) – SuperSpeed USB 3.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com 2 RELATED DOCUMENTS 2.1 TUSB9261 Related Documentation 1. TUSB9260 Implementation Guide (SLLA301) 2.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 3 INTRODUCTION 3.1 System Overview The TUSB9261 is an ARM cortex M3 microcontroller based USB 3.0 to serial ATA bridge. It provides the necessary hardware and firmware to implement a USB attached SCSI protocol (UASP) compliant mass storage device suitable for bridging hard disk drives (HDD), solid state disk drives (SSD), optical drives and other compatible SATA 1.5-Gbps or SATA 3.0-Gbps devices to a USB 3.0 bus.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 ROM www.ti.com GRSTz ARM Cortex M3 VDD3.3 RAM 64 kB VDD1.1 TCK TMS TDO TDI TRST JTAG Data Path RAM 80 kB XI Clock Generation Power and Reset Distribution USB 3.
TUSB9261 www.ti.com 4 OPERATION 4.1 General Functionality SLLSE67F – MARCH 2011 – REVISED JULY 2013 The TUSB9261 ROM contains boot code that executes after a global reset which performs the initial configuration required to load a firmware image from an attached SPI flash memory to local RAM. Once the firmware is loaded it configures the SATA advanced host controller interface host bus adapter (AHCI) and the USB device controller.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 4.2 www.ti.com Firmware Support Default firmware support is provided for the following: • SuperSpeed USB and USB 2.0 High-Speed and Full-Speed • USB Attached SCSI Protocol (UASP) • USB Mass Storage Class (MSC) Bulk-Only Transport (BOT) – Including the 13 Error Cases • USB Mass Storage Specification for Bootability • USB Device Class Definition for Human Interface Devices (HID) – Firmware Update and Custom Functionality (e.g.
TUSB9261 www.ti.com 4.4 SLLSE67F – MARCH 2011 – REVISED JULY 2013 Power Up and Reset Sequence The TUSB9261 does not have specific power sequencing requirements with respect to the core power (VDD), I/O power (VDD33), or analog power (VDDA33). The core power (VDD) or IO power (VDD33) may be powered up for an indefinite period of time while others are not powered up if all of these constraints are met: • All maximum ratings and recommended operating conditions are observed.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 5 www.ti.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Table 5-1. I/O Definitions I/O TYPE DESCRIPTION I Input O Output I/O Input - Output PU Internal pull-up resistor PD Internal pull-down resistor PWR Power signal Table 5-2. Clock and Reset Signals TERMINAL NAME PIN NO. I/O DESCRIPTION GRSTz 4 I PU Global power reset. This reset brings all of the TUSB9261 internal registers to their default states. When GRSTz is asserted, the device is completely nonfunctional.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com Table 5-4. USB Interface Signals TERMINAL PIN NO.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 Table 5-6. JTAG, GPIO, and PWM Signals TERMINAL NAME PIN NO. I/O DESCRIPTION JTAG_TCK 25 I PD JTAG test clock JTAG_TDI 26 I PU JTAG test data in JTAG_TDO 27 O PD JTAG test data out JTAG_TMS 28 I PU JTAG test mode select JTAG_TRSTz 29 I PD JTAG test reset GPIO9/UART_TX 6 I/O PU GPIO/UART transmitter. This terminal can be configured as a GPIO or as the transmitter for a UART channel.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 www.ti.com Table 5-7. Power and Ground Signals TERMINAL NAME PIN NO. I/O DESCRIPTION VDD 1, 12, 19, 32, 33, 41, 47, 49, 55, 61, 63 PWR 1.1-V power rail VDD33 7, 24, 51 PWR 3.3-V power rail VDDA33 34, 40, 48, 62 PWR 3.3-V analog power rail VSSOSC 53 PWR Oscillator ground. If using a crystal, this should not be connected to PCB ground plane. If using an oscillator, this should be connected to PCB ground.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 6 CLOCK CONNECTIONS 6.1 Clock Source Requirements The TUSB9261 supports an external oscillator source or a crystal unit. If a clock is provided to XI instead of a crystal, XO is left open and VSSOSC should be connected to the PCB ground plane. Otherwise, if a crystal is used, the connection needs to follow the guidelines below.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 6.3 www.ti.com Oscillator XI should be tied to the 1.8-V clock source and XO should be left floating. VSSOSC should be connected to the PCB ground plane. A 20-, 25-, 30- or 40-MHz clock can be used. Table 6-1. Oscillator Specification PARAMETER CXI XI input capacitance VIL Low-level input voltage VIH High-level input voltage Ttosc_i Frequency tolerance Tduty Duty cycle TR/TF Rise/Fall time RJ CONDITIONS MIN TYP TJ = 25°C MAX UNIT 0.
TUSB9261 www.ti.com SLLSE67F – MARCH 2011 – REVISED JULY 2013 7 ELECTRICAL SPECIFICATIONS 7.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) VALUE UNIT VDD Steady-state supply voltage –0.3 to 1.4 V VDD33/ VDDA33 Steady-state supply voltage –0.3 to 3.8 V 7.2 Thermal Information TUSB9261 THERMAL METRIC PVP UNITS 64 PINS Junction-to-ambient thermal resistance (1) θJA 30.
TUSB9261 SLLSE67F – MARCH 2011 – REVISED JULY 2013 7.4 www.ti.com DC Electrical Characteristics for 3.3-V Digital I/O over operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT DRIVER TR Rise time 5 pF 1.5 TF Fall time 5 pF 1.53 IOL Low-level output current VDD33 = 3.3 V, TJ = 25°C 6 IOH High-level output current VDD33 = 3.
TUSB9261 www.ti.com 8 SLLSE67F – MARCH 2011 – REVISED JULY 2013 POWER CONSUMPTION Table 8-1. SuperSpeed USB Power Consumption POWER RAIL TYPICAL ACTIVE CURRENT (mA) (1) TYPICAL SUSPEND CURRENT (mA) (2) VDD11 291 153 65 28 VDD33 (1) (2) (3) (3) Transferring data via SS USB to a SSD SATA Gen II device. No SATA power management, U0 only. SATA Gen II SSD attached no active transfer. No SATA power management, U3 only. All 3.3-V power rails connected together. Table 8-2.
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