TVP5146M2 NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Contents 3 ........................................................................................................................ 9 1.1 Features ...................................................................................................................... 9 1.2 Description ................................................................................................................. 10 1.3 Applications ........................
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com .............................................................................................. 93 .................................................................................. 93 3.3 Crystal Specifications ..................................................................................................... 93 3.4 Electrical Characteristics .................................................................................................
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com List of Figures 1-1 Functional Block Diagram ....................................................................................................... 13 1-2 Terminal Assignments Diagram ................................................................................................ 13 2-1 Analog Processors and A/D Converters 2-2 Digital Video Processing Block Diagram ....................................................................
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com List of Tables 1-1 Terminal Functions ............................................................................................................... 14 2-1 Output Format .................................................................................................................... 25 2-2 Summary of Line Frequencies, Data Rates, and Pixel/Line Counts .......................................................
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com ......................................................................... ........................................................................................................... Output Formatter Control 1 Register .......................................................................................... Output Formatter Control 2 Register ..........................................................................................
TVP5146M2 www.ti.com SLES141H – JULY 2005 – REVISED FEBRUARY 2012 ......................................................................................... ................................................................................................. VDP Line Start Register ........................................................................................................ VDP Line Stop Register ........................................................................................................
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 8 List of Tables www.ti.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com NTSC/PAL/SECAM 4×10-Bit Digital Video Decoder With Macrovision™ Detection, YPbPr Inputs, 5-Line Comb Filter, and SCART Support Check for Samples: TVP5146M2 1 Introduction 1.1 Features 1234 • Four 30-MSPS 11-Bit A/D Channels With Programmable Gain Control • Supports NTSC (J, M, 4.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 1.2 www.ti.com Description The TVP5146M2 device is a high-quality single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5146M2 decoder supports the analog-to-digital (A/D) conversion of component RGB and YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-Video into component YCbCr.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 1.3 Applications • • • • • • • • • 1.4 Related Products • • • • • • 1.5 Digital TV LCD TV/monitors DVD-R PVR PC video cards Video capture/video editing Video conferencing Automotive Industrial TVP5150AM1 TVP5151 TVP5154A TVP5158 TVP5160 TVP5147M1 Document Conventions Throughout this data manual, several conventions are used to convey information.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 1.7 www.ti.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 1.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 1.9 www.ti.com Terminal Functions Table 1-1. Terminal Functions TERMINAL NAME NO.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 1-1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION Power Supplies AGND 26 G Analog ground. Connect to analog ground. A18GND_REF 13 G Analog 1.8-V return A18VDD_REF 12 P Analog power for reference 1.8 V CH1_A18GND 79 CH2_A18GND 10 CH3_A18GND 15 G Analog 1.8-V return CH4_A18GND 24 CH1_A18VDD 78 CH2_A18VDD 11 CH3_A18VDD 14 P Analog power. Connect to 1.8 V.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2-1 shows a functional diagram of the analog processors and ADCs. This block provides the analog interface to all video inputs. It accepts up to ten inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.1.1 Video Input Switch Control The TVP5146M2 decoder has four analog channels that accept up to ten video inputs. The user can configure the internal analog video switches via the I2C interface.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com programmed to two formats: 20-bit 4:2:2 with external syncs or 10-bit 4:2:2 with embedded/separate syncs. The circuit detects pseudosync pulses, AGC pulses, and color striping in Macrovision-encoded copy-protected material. Information present in the VBI interval can be retrieved and either inserted in the ITU-R BT.656 output as ancillary data or stored in internal FIFO and/or registers for retrieval via the host port interface.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Peaking CVBS/Y Line Delay Delay Y – Y NTSC/PAL Remodulation SECAM Luma Contrast Brightness Saturation Adjust Notch Filter CVBS SECAM Color Demodulation U Burst Accumulator (V) V CVBS/C NTSC/PAL Demodulation Cr Notch Filter Color LPF ↓2 Burst Accumulator (U) Cb 5-Line Adaptive Comb Filter Color LPF ↓2 Notch Filter Delay Notch Filter Delay U V Figure 2-3.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 2.2.2.1 www.ti.com Color Low-Pass Filter 10 10 0 0 −10 −10 −20 −20 Amplitude − dB Amplitude − dB High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.2.2.2 Y/C Separation Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, chroma trap filters are used which are shown in Figure 2-6 and Figure 2-7. The TI patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 2.2.3 www.ti.com Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2-8 illustrates the basic functions of the luminance data path.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.2.5 Component Video Processor The component video processing block supports a user-selectable contrast, brightness, and saturation adjustment in YCbCr output formats. For YCbCr output formats, gain and offset values are applied to the luma data path to map the pixel values to the correct output range (for 10-bit Ymin = 64 and Ymax = 940), and to provide a means of adjusting contrast and brightness.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com TVP5146M2 TVP5146M2 XTAL1 XTAL1 XTAL2 74 75 74 14.31818-MHz 1.8-V Clock CL1 NC XTAL2 75 14.31818-MHz Crystal R CL2 NOTE: The resistor (R) in parallel with the crystal is recommended to support a wide range of crystal types. A 100-kΩ resistor may be used for most crystal types. Figure 2-12. Reference Clock Configurations 2.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.5 Output Formatter The output formatter sets how the data is formatted for output on the TVP5146M2 output buses. Table 2-1 shows the available output modes. Table 2-1.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 2.5.1 www.ti.com Fast Switches for SCART The TVP5146M2 decoder supports the SCART interface used in European audio/video end equipment to carry composite video, S-Video, and RGB video on the same cable. If composite video and RGB video are present simultaneously on the video terminals assigned to a SCART interface, the TVP5146M2 decoder assumes they are pixel synchronous to each other.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 525 Line 525 1 2 3 4 5 6 7 8 9 10 11 21 22 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 262 263 VBLK Stop 264 265 266 267 268 269 270 271 272 283 284 285 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-14.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 625 Line 622 623 624 625 1 2 3 4 5 6 7 8 23 24 25 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 310 311 VBLK Stop 312 313 314 315 316 317 318 319 320 321 336 337 338 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-15.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 0 DATACLK Y[9:0] Cb Y Cr Y EAV EAV EAV EAV 1 3 4 2 Horizontal Blanking HS Start SAV SAV SAV SAV Cb0 1 2 3 4 Y0 Cr0 Y1 HS Stop HS A C B D AVID AVID Stop AVID Start DATACLK = 2 Pixel Clock Mode A B C D NTSC 601 106 128 42 276 PAL 601 112 128 48 288 NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference Figure 2-16.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 0 DATACLK Y[9:0] Y Y Y Y Horizontal Blanking CbCr[9:0] Cb Cr Cb Cr Horizontal Blanking HS Start Y0 Y1 Y2 Y3 Cb0 Cr0 Cb1 Cr1 HS Stop HS A C B 2 D AVID AVID Stop AVID Start NOTE: AVID rising edge occurs 2 clock cycles early. DATACLK = 1 Pixel Clock Mode A B C D NTSC 601 53 64 19 136 PAL 601 56 64 22 142 NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference Figure 2-17.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com HS First Field B/2 B/2 VS HS H/2 + B/2 Second Field H/2 + B/2 VS 10-Bit (PCLK = 2 Mode Pixel Clock) 20-Bit (PCLK = 1 Pixel Clock) B/2 H/2 B/2 H/2 NTSC 601 64 858 32 429 PAL 601 64 864 32 432 Figure 2-18. VSYNC Position With Respect to HSYNC 2.5.3 Embedded Syncs Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com I2C Host Interface 2.6 Communication with the TVP5146M2 decoder is via an I2C host interface. The I2C standard consists of two signals, the serial input/output data (SDA) line and the serial input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multimastered, the TVP5146M2 decoder functions as a slave device only.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.6.3 VBUS Access The TVP5146M2 decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 2-19 shows the VBUS register access.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 2.6.4 www.ti.com I2C Timing Requirements The TVP5146M2 decoder requires delays in the I2C accesses to accommodate the internal processor timing. In accordance with I2C specifications, the TVP5146M2 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.7.1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is output on the Y_[9:2] terminals during the horizontal blanking period. Table 2-7 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 2.7.2 www.ti.com VBI Raw Data Output The TVP5146M2 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing. This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656 format having only luma data.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com TI recommends the following power-up sequence. Power (1.8 V) 100 µs Power (3.3 V) RESETB (Terminal 34) 3 ms (min) Normal Operation Reset 1 ms (min) SDA (Terminal 29) Invalid I 2C Cycle Valid NOTE: All times shown are minimum values. Maximum time between 1.8 V and 3.3 V should be no longer than 1 second. Figure 2-20. Reset Timing The following register writes must be made before normal operation of the device.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.10 Internal Control Registers The TVP5146M2 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5146M2 is through a standard I2C host port interface, as previously described. Table 2-10 shows the summary of these registers.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-10.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-10.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-10. I2C Register Summary(1) (continued) REGISTER NAME I2C SUBADDRESS DEFAULT R/W Interrupt status 1 F3h Interrupt mask 0 F4h 00h R/W Interrupt mask 1 F5h 00h R/W Interrupt clear 0 F6h 00h R/W Interrupt clear 1 F7h 00h R/W DEFAULT R/W Reserved R/W F8h-FFh Table 2-11.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.11 Register Definitions Table 2-12. Input Select Register Subaddress Default 00h 00h 7 6 5 4 3 Input select [7:0] 2 1 0 Ten input terminals can be configured to support composite, S-Video, and component YPbPr or SCART as listed in Table 2-13. Users must follow this table properly for S-Video and component applications, because only the terminal configurations listed in Table 2-13 are supported. Table 2-13.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-14.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-16. Operation Mode Control Register Subaddress Default 03h 00h 7 6 Reserved 5 4 H-PLL response time 3 2 Reserved 1 0 Power save H-PLL response time 00 = Adaptive (default) 01 = Reserved 10 = Fast 00 = Normal When in the Normal mode, the horizontal PLL (H-PLL) response time is set to its slowest setting.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-18. Color Killer Register Subaddress Default 05h 10h 7 Reserved 6 5 Automatic color killer 4 3 2 Color killer threshold [4:0] 1 0 Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the C terminals are forced to a zero color state 11 = Color killer disabled Color killer threshold [4:0]: 11111 = 31 (maximum) 10000 = 16 (default) 00000 = 0 (minimum) Table 2-19.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-20.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-23. Luminance Contrast Register Subaddress Default 0Ah 80h 7 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS and S-Video luminance. See subaddress 2Fh.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-26. Chrominance Processing Control 1 Register Subaddress Default 0Dh 00h 7 6 Reserved 5 4 Color PLL reset 3 Chroma adaptive comb enable 2 Reserved 1 0 Automatic color gain control [1:0] Color PLL reset: 0 = Color subcarrier PLL not reset (default) 1 = Color subcarrier PLL reset Chrominance adaptive comb enable: This bit is effective on composite video only.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-29. Component Y Contrast Register Subaddress Default 11h 80h 7 6 5 4 3 2 1 0 Y contrast [7:0] Y contrast [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-32. AVID Start Pixel Register Subaddress Default Subaddress 16h 17h 16h-17h 55h 7 6 5 Reserved 4 3 AVID start [7:0] AVID active 2 Reserved 1 0 AVID start [9:8] AVID active: 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK AVID start [9:0]: AVID start pixel number, this is an absolute pixel location from HSYNC start pixel 0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-35. HSYNC Stop Pixel Register Subaddress Default Subaddress 1Ch 1Dh 1Ch-1Dh 040h 7 6 5 4 3 HSYNC stop [7:0] 2 Reserved 1 0 HSYNC stop [9:8] HSYNC stop [9:0]: This is an absolute pixel location from HSYNC start pixel 0. The TVP5146M2 decoder updates the HSYNC stop only when the HSYNC Stop MSB byte is written to.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-39. VBLK Stop Line Register Subaddress Default 24h-25h 015h Subaddress 24h 25h 7 6 5 4 3 VBLK stop [7:0] 2 1 Reserved 0 VBLK stop [9:8] VBLK stop [9:0]: This is an absolute line number. The TVP5146M2 decoder updates the VBLK stop only when the VBLK stop MSB byte is written to. If the user changes these registers, the TVP5146M2 decoder retains values in different modes until this decoder resets.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-42.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-45. CTI Delay Register Subaddress Default 2Dh 00h 7 6 5 Reserved 4 3 2 1 CTI delay [2:0] 0 1 0 CTI delay [2:0]: Sets the delay of the Y channel with respect to Cb/Cr in the CTI block 011 = 3-pixel delay 001 = 1-pixel delay 000 = 0 delay (default) 111 = −1-pixel delay 100 = −4-pixel delay Table 2-46.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-48.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-50.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-52.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-53.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-54.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-56.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-57.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-59. Video Standard Status Register Subaddress 7 Autoswitch 3Fh Read only 6 5 4 3 2 Reserved 1 Video standard [2:0] 0 Autoswitch mode 0 = Stand-alone (forced video standard) mode 1 = Autoswitch mode enabled Video standard [2:0]: CVBS and S-Video Reserved (M, J) NTSC (B, D, G, H, I, N) PAL (M) PAL (Combination-N) PAL NTSC 4.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-61.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-63. AFE Coarse Gain for CH 1 Register Subaddress Default 46h 20h 7 6 5 4 3 2 CGAIN 1 [3:0] 1 0 1 0 Reserved CGAIN 1 [3:0]: Coarse Gain = 0.5 + (CGAIN 1)/10 where 0 ≤ CGAIN 1 ≤ 15 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-65. AFE Coarse Gain for CH 3 Register Subaddress Default 48h 20h 7 6 5 4 3 2 CGAIN 3 [3:0] 1 0 1 0 Reserved CGAIN 3 [3:0]: Coarse Gain = 0.5 + (CGAIN 3)/10 where 0 ≤ CGAIN 3 ≤ 15. This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-67. AFE Fine Gain for Pb_B Register Subaddress Default Subaddress 4Ah 4Bh 4Ah-4Bh 900h 7 6 5 4 3 2 1 0 FGAIN 1 [7:0] Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component B/Pb. Fine Gain = (1/2048) × FGAIN 1, where 0 ≤ FGAIN 1 ≤ 4095 This register is only updated when the MSB (register 4Bh) is written to. This register works only in manual gain control mode.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-70. AFE Fine Gain for CVBS_Luma Register Subaddress Default Subaddress 50h 51h 50h-51h 900h 7 6 5 4 3 2 1 0 FGAIN 4 [7:0] Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: This fine gain applies to CVBS or S-video luma. Fine_Gain = (1/2048) × FGAIN 4, where 0 ≤ FGAIN 4 ≤ 4095 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-71.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-72. Back-End AGC Control Register Subaddress Default 6Ch 08h 7 6 5 4 Reserved 3 1 2 Peak 1 Color 0 Sync This register disables the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst, or composite peak) to decrement the front-end gain.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-76.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-77. F-Bit and V-Bit Control 2 Register Subaddress Default 75h 16h 7 6 Reserved 5 4 Fast lock 3 2 F and V [1:0] 1 Phase detector 0 HPLL Fast lock: Enable fast lock where vertical PLL is reset and a 2-second timer is initialized when vertical lock is lost; during time-out the detected input VSYNC is output.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-80. AGC Increment Speed Register Subaddress Default 78h 06h 7 6 5 Reserved 4 3 2 1 AGC increment speed [2:0] 0 AGC increment speed [2:0]: Adjusts gain increment speed. 111 = 7 (slowest) 110 = 6 (default) ⋮ 000 = 0 (fastest) Table 2-81.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-84. RAM Version LSB Register Subaddress 82h Read only 7 6 5 4 3 RAM version LSB [7:0] 2 1 0 1 0 1 0 Capture RAM version LSB [7:0]: This register identifies the LSB of the RAM code revision number. Example: Patch Release = v08.00.06 ROM Version = 08h RAM Version MSB = 00h RAM Version LSB = 06h Table 2-85.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-88. AGC Decrement Delay Register Subaddress Default 9Eh 1Eh 7 6 5 4 3 AGC decrement delay [7:0] 2 1 0 AGC decrement delay: Number of frames to delay gain decrements 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 Table 2-89.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-90.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 1P1[3] D1[3] 1M1[3] 1P1[2] D1[2] 1M1[2] 1P1[1] D1[1] 1M1[1] 1P1[0] D1[0] 1M1[0] NIBBLE 1 D2[3:0] NIBBLE 2 1P2[3:0] 1M2[3:0] PASS 1 D3[3:0] 1P3[3:0] Filter 1 Enable NIBBLE 3 00 1M3[3:0] D4[3:0] 01 NIBBLE 4 1P4[3:0] PASS 1M4[3:0] 10 D5[3:0] 1P5[3:0] NIBBLE 5 11 1M5[3:0] 2 Filter Logic FILTER 1 D1..D5 PASS 2 2P1..2P5 FILTER 2 2M1..2M5 Filter 2 Enable Figure 2-21. Teletext Filter Function Table 2-91.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-92. VDP FIFO Interrupt Threshold Register Subaddress Default BDh 80h 7 6 5 4 3 2 1 0 1 0 FIFO reset Threshold [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value. Note: 1 word equals 2 bytes. Table 2-93.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-96. VDP Pixel Alignment Register Subaddress Default C2h-C3h 01Eh Subaddress C2h C3h 7 6 5 4 3 Pixel alignment [7:0] 2 1 Reserved 0 Pixel alignment [9:0] Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the program from one line standard to the next line standard.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-100. VDP Full Field Enable Register Subaddress Default D9h 00h 7 6 5 4 Reserved 3 2 1 0 Full field enable Full field enable: 0 = Disabled full field mode(default) 1 = Enabled full field mode This register enables the full field mode.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-105. VBUS Address Register Subaddress Default Subaddress E8h E9h EAh E8h 00h E9h 00h 7 EAh 00h 6 5 4 3 VBUS address [7:0] VBUS address [15:8] VBUS address [23:16] 2 1 0 VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program in these registers the 24-bit address of the internal register to be accessed via host port indirect access mode. Table 2-106.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-107.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-108. Interrupt Status 0 Register Subaddress 7 FIFO THRS F2h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line Interrupt Status 0 and Interrupt Status 1 (see Table 2-109) registers represent the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical AND between the raw status and mask bits.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-109.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-110. Interrupt Mask 0 Register Subaddress 7 FIFO THRS F4h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line The host Interrupt Mask 0 and Interrupt Mask 1 (see Table 2-111) registers can be used by the external processor to mask unnecessary interrupt sources for the Interrupt Status 0 and Interrupt Status 1 register bits, and for the external interrupt terminal.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-111.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-112. Interrupt Clear 0 Register Subaddress 7 FIFO THRS F6h Read only 6 TTX 5 WSS/CGMS 4 VPS/Gemstar 3 VITC 2 CC F2 1 CC F1 0 Line The host Interrupt Clear 0 and Interrupt Clear 1 (see Table 2-113) registers are used by the external processor to clear the interrupt status bits in the host Interrupt Status 0 and Interrupt Status 1 registers.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-113.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 2.12 VBUS Register Definitions Table 2-114. VDP Closed Caption Data Register Subaddress 80 051Ch - 80 051Fh Read only Subaddress 80 051Ch 80 051Dh 80 051Eh 80 051Fh 7 6 5 4 Closed Caption Closed Caption Closed Caption Closed Caption Field Field Field Field 3 1 byte 1 byte 2 byte 2 byte 2 1 0 1 2 1 2 These registers contain the closed caption data arranged in bytes per field. Table 2-115.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-116. VDP VITC Data Register Subaddress Subaddress 80 052Ch 80 052Dh 80 052Eh 80 052Fh 80 0530h 80 0531h 80 0532h 80 0533h 80 0534h 80 052Ch - 80 0534h Read only 7 6 5 4 3 VITC frame byte 1 VITC frame byte 2 VITC seconds byte 1 VITC seconds byte 2 VITC minutes byte 1 VITC minutes byte 2 VITC hours byte 1 VITC hours byte 2 VITC CRC byte 2 1 0 These registers contain the VITC data. Table 2-117.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-119. VDP V-Chip TV Rating Block 3 Register Subaddress 7 None 80 0542h Read only 6 TV-MA 5 TV-14 4 TV-PG 3 TV-G 2 TV-Y7 1 TV-Y 0 None TV Parental Guidelines Rating Block 1 None: No block intended TV-MA: When incoming video program is TV-MA rated in TV Parental Guidelines Rating, this bit is set high. TV-14: When incoming video program is TV-14 rated in TV Parental Guidelines Rating, this bit is set high.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-121.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Table 2-122.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 3 Electrical Specifications 3.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) IOVDD to IOGND DVDD to DGND A33VDD (2) to A33GND (3) (4) Supply voltage range (5) MIN MAX UNIT 0.5 4 V –0.2 2 V –0.3 3.6 V –0.2 2 V VI to DGND Digital input voltage range –0.5 4.5 V VO to DGND Digital output voltage range –0.5 4.5 V AIN to AGND Analog input voltage range –0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 3.4 www.ti.com Electrical Characteristics For minimum/maximum values: IOVDD = 3 V to 3.6 V, AVDD33 = 3 V to 3.6 V, Commercial: AVDD18 = 1.65 V to 1.95 V, DVDD = 1.65 V to 1.95 V, TA = 0°C to 70°C Industrial: AVDD18 = 1.7 V to 1.9 V, DVDD = 1.7 V to 1.9 V, TA = −40°C to 85°C For typical values: IOVDD = AVDD33 = 3.3 V, AVDD18 = DVDD = 1.8 V, TA = 25°C DC Electrical Characteristics (1) 3.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 3.7 Clocks, Video Data, Sync Timing PARAMETER TEST CONDITIONS MIN TYP MAX 45 50 55 Duty cycle, DATACLK t1 High time, DATACLK 18.5 t2 Low time, DATACLK 18.5 t3 Fall time, DATACLK 90% to 10% t4 Rise time, DATACLK t5 Output delay time UNIT % ns ns 4 ns 10% to 90% 4 ns Commercial 10 Industrial 12 ns t2 t1 VOH DATACLK VOL t3 t4 t5 VOH Valid Data Y, C, AVID, VS, HS, FID Valid Data VOL Figure 3-1.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 3.9 www.ti.com Thermal Specifications PARAMETER TEST CONDITIONS (1) MIN TYP MAX UNIT θJA Junction-to-ambient thermal resistance, still air Thermal pad soldered to 4-layer High-K PCB 19.04 °C/W θJC Junction-to-case thermal resistance, still air Thermal pad soldered to 4-layer High-K PCB 0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 4 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5146M2 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 4.1 4.1.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 4.2 4.2.1 www.ti.com Example 2 Assumptions Input connector: S-Video [VI_2_C (luma), VI_1_C (chroma)] 4.2.2 Video format: NTSC (J, M, 443), PAL (B, D, G, H, I, N, Nc, 60), or SECAM (default) Output format: 10-bit ITU-R BT.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 4.3 4.3.1 Example 3 Assumptions Input connector: Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)] 4.3.2 Video format: NTSC (J, M, 443), PAL (B, G, H, I, M, N, Nc) and SECAM Output format: 20-bit 4:2:2 YCbCr with discrete sync outputs Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 20-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 5 Application Information 5.1 Application Example www.ti.com XTAL1 XTAL2 100 kΩ C_0 FID 14.31818 MHz CL2 C_1 C_2 2.2 kΩ HS/CS A3.3VDD CL1 VS/VBLK 2.2 kΩ XTAL2 A1.8VDD IOVDD3.3V C_3 C_4 C_5 XTAL1 DVDD1.8V 80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 VI_1_A 75 Ω (3) 0.1 µF (2) 0.1 µF (3) VI_2A VI_2B VI_2C 75 Ω (3) 0.1 µF (3) VI_3A VI_3B VI_3C 0.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com 5.2 Designing With PowerPAD™ Devices The TVP5146M2 device is housed in a high-performance, thermally-enhanced, 80-terminal PowerPAD package (TI package designator: 80PFP). Use of the PowerPAD package does not require any special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
TVP5146M2 SLES141H – JULY 2005 – REVISED FEBRUARY 2012 www.ti.com Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. REVISION SLES141 COMMENTS Initial release SLES141A Updated Section 2.8 SLES141B Added industrial temperature orderable and updated relevant specifications in Chapter 3 Updated Section 1.2 SLES141C Updated Section 2.11.16, Section 2.11.
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