TVP5146 NTSC/PAL/SECAM 4x10-Bit Digital Video Decoder With Macrovision Detection, YPbPr/RGB Inputs, 5-Line Comb Filter, and SCART Support Data Manual August 2007 Digital Audio Video SLES084C
Contents Section 1 2 Title Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.1 Detailed Functionality . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.2 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.3 Related Products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.4 Ordering Information . . . .
2.11.4 2.11.5 2.11.6 2.11.7 2.11.8 2.11.9 2.11.10 2.11.11 2.11.12 2.11.13 2.11.14 2.11.15 2.11.16 2.11.17 2.11.18 2.11.19 2.11.20 2.11.21 2.11.22 2.11.23 2.11.24 2.11.25 2.11.26 2.11.27 2.11.28 2.11.29 2.11.30 2.11.31 2.11.32 2.11.33 2.11.34 2.11.35 2.11.36 2.11.37 2.11.38 2.11.39 2.11.40 2.11.41 2.11.42 2.11.43 2.11.44 2.11.45 2.11.46 2.11.47 iv Operation Mode Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . Autoswitch Mask Register . . . . . . . . . . . . . . . . . . . . . . . . . . .
2.11.48 2.11.49 2.11.50 2.11.51 2.11.52 2.11.53 2.11.54 2.11.55 2.11.56 2.11.57 2.11.58 2.11.59 2.11.60 2.11.61 2.11.62 2.11.63 2.11.64 2.11.65 2.11.66 2.11.67 2.11.68 2.11.69 2.11.70 2.11.71 2.11.72 2.11.73 2.11.74 2.11.75 2.11.76 2.12 Vertical Line Count Register . . . . . . . . . . . . . . . . . . . . . . . . . . AFE Coarse Gain for CH 1 Register . . . . . . . . . . . . . . . . . . . AFE Coarse Gain for CH 2 Register . . . . . . . . . . . . . . . . . . . AFE Coarse Gain for CH 3 Register . . . . . . .
3 4 5 vi 2.12.2 VDP WSS Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.3 VDP VITC Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.12.4 VDP V-Chip TV Rating Block 1 Register . . . . . . . . . . . . . . . 2.12.5 VDP V-Chip TV Rating Block 2 Register . . . . . . . . . . . . . . . 2.12.6 VDP V-Chip TV Rating Block 3 Register . . . . . . . . . . . . . . . 2.12.7 VDP V-Chip MPAA Rating Data Register . . . . . . . . . . . . . . . 2.12.
List of Illustrations Figure 1−1 1−2 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 2−13 2−14 2−15 2−16 2−17 2−18 2−19 2−20 2−21 2−22 2−23 2−24 2−25 2−26 2−27 3−1 Title Page Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Terminal Assignments Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Analog Processors and A/D Converters . . . . . . . . . . . . . . . . . . . . . . . . . . . .
3−2 5−1 I2C Host Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 93 List of Tables Table 1−1 2−1 2−2 2−3 2−4 2−5 2−6 2−7 2−8 2−9 2−10 2−11 2−12 viii Title Page Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Output Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
1 Introduction The TVP5146 device is a high quality, single-chip digital video decoder that digitizes and decodes all popular baseband analog video formats into digital component video. The TVP5146 decoder supports the analog-to-digital (A/D) conversion of component RGB and YPbPr signals, as well as the A/D conversion and decoding of NTSC, PAL, and SECAM composite and S-video into component YCbCr. This decoder includes four 10-bit 30-MSPS A/D converters (ADCs).
1.1 • Component processor • Clock/timing processor and power-down control • Software-controlled power-saving standby mode • Output formatter • I2C host port interface • VBI data processor • Macrovision copy protection detection circuit (Type 1, 2, 3, and separate color stripe detection) • 3.3-V tolerant digital I/O ports Detailed Functionality • Four 30-MSPS, 10-bit A/D channels with programmable gain control • Supports NTSC (J, M, 4.
• 1.2 1.3 − Teletext (NABTS, WST) − CC and extended data service (EDS) − Wide screen signaling (WSS) − Copy generation management system (CGMS) − Video program system (VPS/PDC) − Vertical interval time code (VITC) − Gemstar 1×/2× electronic program guide compatible mode − Register readback of CC, WSS (CGMS), VPS/PDC, VITC, and Gemstar 1×/2× sliced data • I2C host port interface • Reduced power consumption: 1.8-V digital core, 3.3-V for digital I/O, and 1.
1.
1.
1.7 Terminal Functions Table 1−1.
Table 1−1. Terminal Functions (Continued) TERMINAL NAME NUMBER I/O DESCRIPTION Host Interface I2C clock input SCL 28 I SDA 29 I/O AGND 26 I Analog ground. Connect to analog ground. A18GND_REF 13 I Analog 1.8-V return A18VDD_REF 12 I Analog power for reference 1.8 V CH1_A18GND CH2_A18GND CH3_A18GND CH4_A18GND 79 10 15 24 I Analog 1.8-V return CH1_A18VDD CH2_A18VDD CH3_A18VDD CH4_A18VDD 78 11 14 25 I Analog power. Connect to 1.8 V.
8 TVP5146 SLES084C − August 2007
2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2−1 shows a functional diagram of the analog processors and ADCs. This block provides the analog interface to all video inputs. It accepts up to 10 inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal.
2.1.2 Analog Input Clamping An internal clamping circuit restores the ac-coupled video signal to a fixed dc level. The clamping circuit provides line-by-line restoration of the video sync level to a fixed dc reference voltage. The selection between bottom and mid clamp is performed automatically by the TVP5146 decoder. 2.1.3 Automatic Gain Control The TVP5146 decoder uses four programmable gain amplifiers (PGAs), one per channel. The PGA can scale a signal with a voltage-input compliance of 0.
Copy Protection Detector VBI Data Processor Slice VBI Data Y[9:0] Output Formatter CH1 A/D 2 Decimation CVBS/Y/G FSS CVBS/Y CH2 A/D 2 Decimation C CH3 A/D 2 Decimation Y/G CH4 A/D C[9:0] Pb/B Composite Processor YCbCr Component Processor YCbCr Pr/R 2 Decimation XTAL1 FID XTAL2 RESETB PWDN DATACLK VS/VBLK Timing Processor HS/CS Host Interface SCL SDA GLCO AVID Figure 2−2. Digital Video Processor Block Diagram 2.2.
Peaking CVBS/Y Line Delay Delay Y – Y NTSC/PAL Remodulation SECAM Luma Contrast Brightness Saturation Adjust Notch Filter CVBS SECAM Color Demodulation U Burst Accumulator (V) V CVBS/C NTSC/PAL Demodulation Color LPF ↓2 Cr Notch Filter Color LPF ↓2 Burst Accumulator (U) Cb 5-Line Adaptive Comb Filter Notch Filter Delay Notch Filter Delay U V Figure 2−3.
2.2.2.1 Color Low-Pass Filter High filter bandwidth preserves sharp color transitions and produces crisp color boundaries. However, for video sources that have asymmetrical U and V side bands, it is desirable to limit the filter bandwidth to avoid UV crosstalk. The color low-pass filter bandwidth is programmable to enable one of the three notch filters. Figure 2−4 through Figure 2−7 represent the frequency responses of the wideband color low-pass filters. 10 10 0 0 PAL SQP –3 dB @ 1.
2.2.2.2 Y/C Separation Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma trap filters are used which are shown in Figure 2−8 through Figure 2−11. TI’s patented adaptive comb filter algorithm reduces artifacts such as hanging dots at color boundaries.
2.2.3 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal. The luminance signal is then fed into the input of a peaking circuit. Figure 2−12 illustrates the basic functions of the luminance data path. In the case of S-video, the luminance signal bypasses the comb filter or chroma trap filter and is fed directly to the circuit.
7 Peak at f = 2.89 MHz 6 Gain = 2 5 Amplitude − dB Gain = 1 4 3 Gain = 0.5 2 1 0 Gain = 0 −1 0 1 2 3 4 5 6 7 f – Frequency – MHz Figure 2−15. Peaking Filter Response, PAL Square Pixel Sampling 2.2.3.1 Color Transient Improvement Color transient improvement (CTI) enhances horizontal color transients by delay modulation for both color difference signals. The operation must be performed only on YCbCr-formatted data.
For CbCr components, a saturation (gain) factor is applied to the CbCr inputs in order to map them to the CbCr output code range and provide saturation control. Similarly, the limit block can limit CbCr outputs to a valid range: Cb,Crmin = 64 / Cb,Crmax = 960 CbCr x Limit CbCr Gain Figure 2−17. CbCr Component Gain, Offset, Limit 2.2.5 Color Space Conversion The formulas for RGB to YCbCr conversion are given as: Y = 0.299 × R + 0.587 × G + 0.114 × B Cb = –0.172 × R – 0.339 × G + 0.511 × B + 512 Cr = 0.
The instantaneous frequency of the color subcarrier can be calculated from the following equation: F PLL + F ctrl 2 23 F sclk where FPLL is the frequency of the subcarrier PLL, Fctrl is the 23-bit PLL frequency control word, and Fsclk is two times the pixel frequency. Figure 2−19 shows the detailed timing diagram.
Table 2−2. Summary of Line Frequencies, Data Rates, and Pixel/Line Counts PIXELS PER LINE ACTIVE PIXELS PER LINE LINES PER FRAME PIXEL FREQUENCY (MHz) NTSC-J, M 858 720 525 NTSC-4.43 858 720 525 PAL-M 858 720 PAL-60 858 PAL-B, D, G, H, I 864 PAL-N PAL-Nc STANDARDS COLOR SUBCARRIER FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz) 13.5 3.579545 15.73426 13.5 4.43361875 15.73426 525 13.5 3.57561149 15.73426 720 525 13.5 4.43361875 15.73426 720 625 13.5 4.43361875 15.
525-Line 525 1 2 3 4 5 6 7 8 9 10 11 21 22 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 262 263 VBLK Stop 264 265 266 267 268 269 270 271 272 273 284 285 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 VBLK Stop Figure 2−20.
625-Line 622 623 624 625 1 2 3 4 5 6 7 8 23 24 25 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 310 311 VBLK Stop 312 313 314 315 316 317 318 319 320 321 336 337 338 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start NOTE: Line numbering conforms to ITU-R BT.470 VBLK Stop Figure 2−21.
0 DATACLK Y[9:0] Cb Y Cr Y EAV EAV EAV EAV 2 1 3 4 Horizontal Blanking HS Start SAV SAV SAV SAV Cb0 1 2 3 4 Y0 Cr0 Y1 HS Stop HS A C B D AVID AVID Stop AVID Start DATACLK = 2 Pixel Clock Mode A B C D NTSC 601 106 128 42 276 PAL 601 112 128 48 288 NTSC Sqp 108 128 44 280 PAL Sqp 144 128 80 352 NOTE: ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference Figure 2−22.
0 DATACLK Y[9:0] CbCr[9:0] Y Y Y Y Horizontal Blanking Cb Cr Cb Cr Horizontal Blanking HS Start Y0 Y1 Y2 Y3 Cb0 Cr0 Cb1 Cr1 HS Stop HS A C B 2 D AVID AVID Stop AVID Start NOTE: AVID rising edge occurs 2 clock cycles early. DATACLK = 1 Pixel Clock Mode A B C D NTSC 601 53 64 19 136 PAL 601 56 64 22 142 NTSC Sqp 54 64 20 138 PAL Sqp 72 64 38 174 NOTE: 20-bit 4:2:2 timing with 1× pixel clock reference Figure 2−23.
HS First Field B/2 B/2 VS HS H/2 + B/2 Second Field H/2 + B/2 VS 10-Bit (PCLK = 2 Mode Pixel Clock) 20-Bit (PCLK = 1 Pixel Clock) B/2 H/2 B/2 H/2 NTSC 601 64 858 32 429 PAL 601 64 864 32 432 NTSC Sqp 64 780 32 390 PAL Sqp 64 944 32 472 Figure 2−24. VSYNC Position With Respect to HSYNC 2.5.3 Embedded Syncs Standards with embedded syncs insert the SAV and EAV codes into the data stream on the rising and falling edges of AVID.
Because SDA and SCL are kept open-drain at a logic-high output level or when the bus is not driven, the user must connect SDA and SCL to a positive supply voltage via a pullup resistor on the board. The slave-address select signal, terminal 37 (I2CA), enables the use of two TVP5146 decoders tied to the same I2C bus by controlling the least significant bit of the I2C device address. Table 2−4.
I2C Registers VBUS Registers 00h HOST Processor 00 0000h I2C CC 80 051Ch WSS 80 0520h VITC E0h VBUS Data E1h E8h Line Mode VBUS[23:0] VPS VBUS Address EAh FIFO FFh 80 052Ch 80 0600h 80 0700h 90 1904h FF FFFFh VBUS Write Single Byte S B8 ACK E8 ACK VA0 ACK VA1 ACK S B8 ACK E0 ACK Send Data ACK P VA2 ACK P ACK P Multiple Bytes S B8 ACK E8 ACK VA0 ACK VA1 ACK VA2 S B8 ACK E1 ACK Send Data ACK ••• Send Data VA0 VA1 ACK VA2 ACK P VBUS Read Single Byt
2.6.4 I 2C Timing Requirements The TVP5146 decoder requires delays in the I2C accesses to accommodate the internal processor timing. In accordance with I2C specifications, the TVP5146 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required.
2.7.1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode. VBI data is output on the Y[9:2] terminals during the horizontal blanking period. Table 2−7 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of the FIFO is 512 bytes. Therefore, the FIFO can store up to 11 lines of teletext data with the NTSC NABTS standard.
2.7.2 VBI Raw Data Output The TVP5146 decoder can output raw A/D video data at twice the sampling rate for external VBI slicing. This is transmitted as an ancillary data block, although somewhat differently from the way the sliced VBI data is transmitted in the FIFO format as described in Section 2.7.1. The samples are transmitted during the active portion of the line. VBI raw data uses ITU-R BT.656 format having only luma data. The chroma samples are replaced by luma samples.
The TVP5146 requires that terminal 69 (C_1/GPIO) be held LOW. If using the 20-/16-bit mode or using this terminal as GPIO, then this terminal must be pulled low through a 2.2-kΩ pulldown resistor (see Figure 5−1). If unused, this terminal can be shorted to ground. (Note: If using the 20-/16-bit mode and only using the 16 MSBs, it is possible to short terminal 69 to GND, but the current for IOVDD will increase by 2 or 3 mA.
Table 2−10.
Table 2−10.
Table 2−10.
Table 2−10. Registers Summary (Continued) REGISTER NAME I2C SUBADDRESS DEFAULT R/W Interrupt status 0 F2h Interrupt status 1 F3h Interrupt mask 0 F4h 00h R/W Interrupt mask 1 F5h 00h R/W Interrupt clear 0 F6h 00h R/W Interrupt clear 1 F7h 00h R/W DEFAULT R/W Reserved R/W R/W F8h–FFh NOTE: R = Read only W = Write only R/W = Read and write Reserved register addresses must not be written to. Table 2−11.
2.11 Register Definitions 2.11.1 Input Select Register Subaddress 00h Default 00h 7 6 5 4 3 2 1 0 Input select [7:0] Table 2−12.
2.11.2 AFE Gain Control Register Subaddress 01h Default 0Fh 7 6 5 4 Reserved 3 2 1 0 1 1 AGC chroma AGC luma Bit 3: 1 must be written to this bit. Bit 2: 1 must be written to this bit. AGC chroma: Controls automatic gain in the chroma/B/R/PbPr channel: 0 = Manual (if AGC luma is set to manual, AGC chroma is forced to be in manual) 1 = Enabled auto gain, applies a gain value acquired from the sync channel for S-video and component mode. When AGC luma is set, this state is valid.
2.11.4 Operation Mode Register Subaddress 03h Default 00h 7 6 5 4 3 2 1 Reserved 0 Power save Power save: 0 = Normal operation (default) 1 = Power-save mode. Reduces the clock speed of the internal processor and switches off the ADCs. I2C interface is active and all current operating settings are preserved. 2.11.5 Autoswitch Mask Register Subaddress 04h Default 23h 7 6 Reserved 5 4 3 2 1 0 SECAM NTSC 4.
2.11.6 Color Killer Register Subaddress 05h Default 10h 7 6 Reserved 5 4 3 2 Automatic color killer 1 0 Color killer threshold [4:0] Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the C terminals are forced to a zero color state. 11 = Color killer disabled Color killer threshold [4:0]: 1 1111 = 31 (maximum) 1 0000 = 16 (default) 0 0000 = 0 (minimum) 2.11.
2.11.8 Luminance Processing Control 2 Register Subaddress 07h Default 00h 7 6 5 Luma filter select [1:0] 4 3 Reserved 2 1 Peaking gain (sharpness) [1:0] 0 Reserved Luma filter selected [1:0]: 00 = Luminance adaptive comb enabled (default on CVBS) 01 = Luminance adaptive comb disabled (trap filter selected) 10 = Luma comb/trap filter bypassed (default on S-video, component mode, and SECAM) 11 = Reserved Peaking gain (sharpness) [1:0]: 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 2.11.
2.11.11 Luminance Contrast Register Subaddress 0Ah Default 80h 7 6 5 4 3 2 1 0 1 0 1 0 Contrast [7:0] Contrast [7:0]: This register works for CVBS and S-video luminance. 1111 1111 = 255 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) 2.11.12 Chrominance Saturation Register Subaddress 0Bh Default 80h 7 6 5 4 3 2 Saturation [7:0] Saturation [7:0]: This register works for CVBS and S-video chrominance.
2.11.14 Chrominance Processing Control 1 Register Subaddress 0Dh Default 00h 7 6 5 Reserved 4 3 2 Color PLL reset Chrominance adaptive comb enable Reserved 1 0 Automatic color gain control [1:0] Color PLL reset: 0 = Color subcarrier PLL not reset (default) 1 = Color subcarrier PLL reset Chrominance adaptive comb enable: This bit is effective on composite video only.
2.11.17 Component Y Contrast Register Subaddress 11h Default 80h 7 6 5 4 3 2 1 0 Y contrast [7:0] Y contrast [7:0]: This register works only with YPbPr component video. For RGB video, user must use the AFE gain registers.
2.11.18 Component Pb Saturation Register Subaddress 12h Default 80h 7 6 5 4 3 2 1 0 Pb saturation [7:0] Pb saturation [7:0]: This register works only with YPbPr component video. For RGB video, user must use the AFE gain registers. 1111 1111 = 255 (maximum) 1000 0000 =128 (default) 0000 0000 = 0 (minimum) 2.11.19 Component Y Brightness Register Subaddress 14h Default 80h 7 6 5 4 3 2 1 0 Y brightness [7:0] Y brightness [7:0]: This register works only with YPbPr component video.
2.11.21 AVID Stop Pixel Register Subaddress 18h–19h Default 325h Subaddress 7 6 5 4 18h 3 2 1 0 AVID stop [7:0] 19h Reserved AVID stop [9:8] AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location from HSYNC start pixel 0. NTSC 601 805 (325h) default NTSC Sqp 726 (2D6h) PAL 601 808 (328h) PAL Sqp 696 (2B8h) The TVP5146 decoder updates the AVID stop only when the AVID stop MSB byte is written to.
2.11.24 VSYNC Start Line Register Subaddress 1Eh–1Fh Default 004h Subaddress 7 6 5 4 1Eh 3 2 1 0 VSYNC start [7:0] 1Fh Reserved VSYNC start [9:8] VSYNC start [9:0]: This is an absolute line number. The TVP5146 decoder updates the VSYNC start only when the VSYNC start MSB byte is written to. If the user changes these registers, then the TVP5146 decoder retains values in different modes until this decoder resets. NTSC: default 004h, PAL: default 001h 2.11.
2.11.
2.11.31 CTI Delay Register Subaddress 2Dh Default 00h 7 6 5 4 3 2 Reserved 1 0 CTI delay [2:0] CTI delay [2:0]: Sets the delay of the Y channel with respect to Cb/Cr in the CTI block 011 = 3 pixel delay 001 = 1 pixel delay 000 = 0 delay (default) 111 = –1 pixel delay 100 = –4 pixel delay 2.11.
2.11.
2.11.36 Output Formatter 2 Register Subaddress 34h Default 00h 7 6 5 4 Reserved 3 Y[9:0] enable 2 Reserved 1 0 CLK polarity Clock enable 1 0 Y[9:0] enable: Y[9:0] and C[9:0] output enable 0 = Y[9:0] and C[9:0] high impedance (default) 1 = Y [9:0] and C[9:0] active CLK polarity: 0 = Data clocked out on the falling edge of DATACLK (default) 1 = Data clocked out on the rising edge of DATACLK Clock enable: 0 = DATACLK outputs are high-impedance (default). 1 = DATACLK outputs are enabled.
2.11.38 Output Formatter 4 Register Subaddress 36h Default FFh 7 6 VS/VBLK [1:0] 5 4 HS/CS [1:0] 3 2 C_1 [1:0] 1 0 C_0 [1:0] VS/VBLK [1:0]: VS terminal function select 00 = VS is logic 0 output. 01 = VS is logic 1 output. 10 = VS/VBLK is vertical sync or vertical blank output corresponding to bit 1 (VS/VBLK) in the sync control register at subaddress 32h (see Section 2.11.34). 11 = VS is logic input (default). HS/CS [1:0]: HS terminal function select 00 = HS is logic 0 output.
2.11.39 Output Formatter 5 Register Subaddress 37h Default FFh 7 6 C_5 [1:0] 5 4 C_4 [1:0] 3 2 C_3 [1:0] 1 0 C_2 [1:0] C_5 [1:0]: C_5 terminal function select 00 = C_5 is logic 0 output. 01 = C_5 is logic 1 output. 10 = Reserved 11 = C_5 is logic input (default). C_4 [1:0]: C_4 terminal function select 00 = C_4 is logic 0 output. 01 = C_4 is logic 1 output. 10 = Reserved 11 = C_4 is logic input (default). C_3 [1:0]: C_3 terminal function select 00 = C_3 is logic 0 output.
2.11.40 Output Formatter 6 Register Subaddress 38h Default FFh 7 6 5 C_9 [1:0] 4 3 C_8 [1:0] 2 1 C_7 [1:0] 0 C_6 [1:0] C_9 [1:0]: C_9 terminal function select 00 = C_9 is logic 0 output. 01 = C_9 is logic 1 output. 10 = Reserved 11 = C_9 is logic input (default). C_8 [1:0]: C_8 terminal function select 00 = C_8 is logic 0 output. 01 = C_8 is logic 1 output. 10 = Reserved 11 = C_8 is logic input (default). C_7 [1:0]: C_7 terminal function select 00 = C_7 is logic 0 output.
2.11.42 Status 1 Register Subaddress 3Ah Read only 7 6 5 4 3 2 1 0 Peak white detect status Line-alternating status Field rate status Lost lock detect Color subcarrier lock status Vertical sync lock status Horizontal sync lock status TV/VCR status Peak white detect status: 0 = Peak white is not detected. 1 = Peak white is detected.
2.11.43 Status 2 Register Subaddress 3Bh Read only 7 6 5 4 3 Reserved Weak signal detection PAL switch polarity Field sequence status Reserved 2 1 0 Macrovision detection [2:0] Weak signal detection: 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field: 0 = PAL switch is zero. 1 = PAL switch is one.
2.11.45 Video Standard Status Register Subaddress 3Fh Read only 7 6 5 Autoswitch 4 3 2 Reserved 1 0 Video standard [2:0] Autoswitch mode: 0 = Stand-alone (forced video standard) mode 1 = Autoswitch mode Video standard [2:0]: CVBS and S-video 000 = Reserved 001 = (M, J) NTSC 010 = (B, D, G, H, I, N) PAL 011 = (M) PAL 100 = (Combination-N) PAL 101 = NTSC 4.
2.11.47 GPIO Input 2 Register Subaddress 41h Read only 7 6 5 4 3 2 1 0 FSS AVID GLCO VS HS FID C_9 C_8 FSS input terminal status: 0 = Input is a low. 1 = Input is a high. AVID input terminal status: 0 = Input is a low. 1 = Input is a high. GLCO input terminal status: 0 = Input is a low 1 = Input is a high. VS input terminal status: 0 = Input is a low. 1 = Input is a high. HS input status: 0 = Input is a low. 1 = Input is a high. FID input status: 0 = Input is a low.
2.11.49 AFE Coarse Gain for CH 1 Register Subaddress 46h Default 20h 7 6 5 4 3 2 CGAIN 1 [3:0] 1 0 Reserved CGAIN 1 [3:0]: Coarse_Gain = 0.5 + (CGAIN 1)/10, where 0 CGAIN 1 15 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.5 2.11.
2.11.51 AFE Coarse Gain for CH 3 Register Subaddress 48h Default 20h 7 6 5 4 3 2 CGAIN 3 [3:0] 1 0 Reserved CGAIN 3 [3:0]: Coarse_Gain = 0.5 + (CGAIN 3)/10, where 0 CGAIN 3 15 This register works only in the manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 1100 = 1.7 1011 = 1.6 1010 = 1.5 1001 = 1.4 1000 = 1.3 0111 = 1.2 0110 = 1.1 0101 = 1 0100 = 0.9 0011 = 0.8 0010 = 0.7 (default) 0001 = 0.6 0000 = 0.5 2.11.
2.11.53 AFE Fine Gain for Pb_B Register Subaddress 4Ah–4Bh Default 900h Subaddress 7 6 5 4 4Ah 3 2 1 0 FGAIN 1 [7:0] 4Bh Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component Pb/B. Fine_Gain = (1/2048) * FGAIN 1, where 0 FGAIN 1 4095 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.
2.11.55 AFE Fine Gain for R_Pr Register Subaddress 4Eh–4Fh Default 900h Subaddress 7 6 5 4 4Eh 3 2 1 0 FGAIN 3 [7:0] 4Fh Reserved FGAIN 3 [11:8] FGAIN 3 [11:0]: This fine gain applies to component Pb/B. Fine_Gain = (1/2048) * FGAIN 3, where 0 FGAIN 3 4095 This register works only in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 1111 1111 = 1.9995 1100 0000 0000 = 1.5 1001 0000 0000 = 1.125 (default) 1000 0000 0000 = 1 0100 0000 0000 = 0.
2.11.58 AGC White Peak Processing Register Subaddress 74h Default 00h 7 6 5 4 3 2 1 0 Luma peak A Reserved Color burst A Sync height A Luma peak B Composite peak Color burst B Sync height B Luma peak A: Use of the luma peak as a video amplitude reference for the back-end feed-forward type AGC algorithm. 0 = Enabled (default) 1 = Disabled Color burst A: Use of the color burst amplitude as a video amplitude reference for the back-end.
Luma peak B: Use of the luma peak as a video amplitude reference for the front-end feedback type AGC algorithm. 0 = Enabled (default) 1 = Disabled Composite peak: Use of the composite peak as a video amplitude reference for the front-end feedback type AGC algorithm. NOTE: Required for CVBS and SCART (with color burst) video sources. 0 = Enabled (default) 1 = Disabled Color burst B: Use of the color burst amplitude as a video amplitude reference for the front-end feedback type AGC algorithm.
2.11.60 AGC Increment Delay Register Subaddress 79h Default 1Eh 7 6 5 4 3 2 1 0 1 0 AGC increment delay [7:0] AGC increment delay: Number of frames to delay gain increments 1111 1111 = 255 L 0001 1110 = 30 (default) L 0000 0000 = 0 2.11.61 Subaddress Chip ID MSB Register 80h Read only 7 6 5 4 3 2 Chip ID MSB [7:0] Chip ID MSB [7:0]: This register identifies the MSB of the device ID. Value = 51h 2.11.
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2.11.64 VDP TTX Filter Control Register Subaddress BBh Default 00h 7 6 5 Reserved 4 3 Filter logic [1:0] 2 1 0 Mode TTX filter 2 enable TTX filter 1 enable Filter logic [1:0]: Allows different logic to be applied when combining the decision of filter 1 and filter 2 as follows: 00 = NOR (default) 01 = NAND 10 = OR 11 = AND Mode: Indicates which teletext mode is in use.
1P1[3] D1[3] 1M1[3] 1P1[2] D1[2] 1M1[2] 1P1[1] D1[1] 1M1[1] 1P1[0] D1[0] 1M1[0] NIBBLE 1 D2[3:0] NIBBLE 2 1P2[3:0] 1M2[3:0] PASS 1 D3[3:0] 1P3[3:0] Filter 1 Enable NIBBLE 3 00 1M3[3:0] D4[3:0] 01 NIBBLE 4 1P4[3:0] PASS 1M4[3:0] 10 D5[3:0] 1P5[3:0] NIBBLE 5 11 1M5[3:0] 2 Filter Logic FILTER 1 D1..D5 PASS 2 FILTER 2 2P1..2P5 2M1..2M5 Filter 2 Enable Figure 2−27. Teletext Filter Function 2.11.
2.11.66 VDP FIFO Interrupt Threshold Register Subaddress BDh Default 80h 7 6 5 4 3 2 1 0 Threshold [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value. NOTE: 1 word equals 2 bytes. 2.11.67 VDP FIFO Reset Register Subaddress BFh Default 00h 7 6 5 4 3 2 1 Reserved 0 FIFO reset FIFO reset: Writing any data to this register clears the FIFO and VDP data registers (CC, WSS, VITC and VPS).
2.11.70 VDP Pixel Alignment Register Subaddress C2h–C3h Default 01Eh Subaddress 7 6 5 4 C2h 3 2 1 0 Pixel alignment [7:0] C3h Reserved Pixel alignment [9:8] Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller initiates the program from one line standard to the next line standard. For example, the previous line of teletext to the next line of closed caption.
2.11.74 VDP Full Field Enable Register Subaddress D9h Default 00h 7 6 5 4 3 2 1 0 Reserved Full field enable Full field enable: 0 = Disabled full field mode (default) 1 = Enabled full field mode This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh.
2.11.78 FIFO Read Data Register Subaddress E2h Read only 7 6 5 4 3 2 1 0 FIFO read data [7:0] FIFO read data [7:0]: This register is provided to access VBI FIFO data through the host port. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from registers or from the FIFO.
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2.11.81 Interrupt Raw Status 1 Register Subaddress F1h Read only 7 6 5 4 3 Reserved 2 1 0 Macrovision status changed Standard changed FIFO full Macrovision status changed: unmasked 0 = Macrovision status unchanged 1 = Macrovision status changed Standard changed: unmasked 0 = Video standard unchanged 1 = Video standard changed FIFO full: unmasked 0 = FIFO not full 1 = FIFO was full during write to FIFO The FIFO full error flag is set when the current line of VBI data cannot enter the FIFO.
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2.12 VBUS Register Definitions 2.12.1 VDP Closed Caption Data Register Subaddress 80 051Ch–80 051Fh Read only Subaddress 7 6 5 4 3 80 051Ch Closed caption field 1 byte 1 80 051Dh Closed caption field 1 byte 2 80 051Eh Closed caption field 2 byte 1 80 051Fh Closed caption field 2 byte 2 2 1 0 These registers contain the closed caption data arranged in bytes per field. 2.12.
2.12.3 VDP VITC Data Register Subaddress 80 052Ch–80 0534h Read only Subaddress 7 6 5 4 3 80 052Ch VITC frame byte 1 80 052Dh VITC frame byte 2 80 052Eh VITC seconds byte 1 80 052Fh VITC seconds byte 2 80 0530h VITC minutes byte 1 80 0531h VITC minutes byte 2 80 0532h VITC hours byte 1 80 0533h VITC hours byte 2 80 0534h VITC CRC byte 2 1 0 These registers contain the VITC data. 2.12.
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2.12.9 VDP VPS/Gemstar Data Register Subaddress 80 0700h–80 070Ch VPS: Read only Subaddress 7 6 5 4 3 80 0700h VPS byte 1 80 0701h VPS byte 2 80 0702h VPS byte 3 80 0703h VPS byte 4 80 0704h VPS byte 5 80 0705h VPS byte 6 80 0706h VPS byte 7 80 0707h VPS byte 8 80 0708h VPS byte 9 80 0709h VPS byte 10 80 070Ah VPS byte 11 80 070Bh VPS byte 12 80 070Ch VPS byte 13 2 1 0 These registers contain the entire VPS data line except the clock run-in code or the start code.
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3 Electrical Specifications 3.1 Absolute Maximum Ratings† Supply voltage range: IOVDD to I/O GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 0.5 V to 4 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.2 V to 2 V A33VDD (see Note 1) to A18GND (see Note 2) . . . . . . . . . . . . . . . . −0.3 V to 3.6 V A18VDD (see Note 3) to A33GND (see Note 4) . . . . . . . . . . . . . . . . . . −0.
3.3 Electrical Characteristics For minimum/maximum values: IOVDD = 3.0 V to 3.6 V, DVDD = 1.65 V to 1.95 V, AVDD33 = 3.0 V to 3.6 V, AVDD18 = 1.65 V to 1.95 V, TA = 0°C to 70°C For typical values: IOVDD = 3.3 V, DVDD = 1.8 V, AVDD33 = 3.3 V, AVDD18 = 1.8 V, TA = 25°C 3.3.1 DC Electrical Characteristics PARAMETER TEST CONDITIONS MIN TYP CVBS 6 RGB and CVBS 6 IDDIO(D) 3 3 V IO digital supply current 3.3-V IDD(D) 1 8 V digital supply current 1.8-V IDD33(A) 3 3 V analog supply current 3.
3.3.3 Timing 3.3.3.1 Clocks, Video Data, Sync Timing TEST CONDITIONS (see Note 1) PARAMETER Duty cycle DATACLK MIN TYP MAX 45% 50% 55% UNIT t1 High time, DATACLK 18.5 ns t2 Low time, DATACLK 18.5 ns t3 Fall time, DATACLK 90% to 10% 4 ns t4 Rise time, DATACLK 10% to 90% 4 ns t5 Output delay time 10 ns NOTE 1: CL = 15 pF t2 t1 VOH DATACLK VOL t3 t4 VOH Y, C, AVID, VS, HS, FID Valid Data Valid Data VOL t5 Figure 3−1.
3.3.3.2 I2C Host Port Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT µs t1 Bus free time between STOP and START t2 Data hold time 1.3 t3 Data setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 ns t6 Hold time (repeated) START condition 0.
4 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5146 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 4.1 Example 1 4.1.
4.2 Example 2 4.2.1 Assumptions Input connector: S-video [VI_2_C (luma), VI_1_C (chroma)] Video format: NTSC (J, M, 443), PAL (B, G, H, I, M, N, Nc) and SECAM Output format: 10-bit 4:2:2 YCbCr with discrete sync outputs 4.2.2 Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 10-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above.
4.3 Example 3 4.3.1 Assumptions Input connector: Component [VI_1_B (Pb), VI_2_B (Y), VI_3_B (Pr)] Video format: NTSC (J, M, 443), PAL (B, G, H, I, M, N, Nc) and SECAM Output format: 20-bit 4:2:2 YCbCr with discrete sync outputs 4.3.2 Recommended Settings Recommended I2C writes: This setup requires additional writes to output the discrete sync 20-bit 4:2:2 data, HS, and VS, and to autoswitch between all video formats mentioned above.
92 TVP5146 SLES084C − August 2007
5 Application Information 5.1 Application Example XTAL1 C_0 FID XTAL2 14.31818 MHz C_1 C_2 2.2 kΩ HS/CS A3.3VDD CL2 CL1 VS/VBLK 2.2 kΩ XTAL2 A1.8VDD IOVDD3.3V C_3 C_4 C_5 XTAL1 DVDD1.8V 75 Ω (3) 0.1 µF (2) 0.1 µF (3) VI_2A VI_2B VI_2C 75 Ω (3) 0.1 µF (3) VI_3A VI_3B VI_3C 75 Ω (3) 0.
5.2 Designing With PowerPADt Devices The TVP5146 device is housed in a high-performance, thermally enhanced, 80-terminal PowerPAD package (TI package designator: 80PFP). Use of the PowerPAD package does not require any special considerations except to note that the thermal pad, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device TVP5146PFPR Package Package Pins Type Drawing HTQFP PFP 80 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 24.4 Pack Materials-Page 1 15.0 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 15.0 1.5 20.0 24.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5146PFPR HTQFP PFP 80 1000 367.0 367.0 45.
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