Datasheet

Composite and S-V ideo Processor
Y/C
Separation
5-line
Adaptive
Comb
Luma
Processing
Chroma
Processing
M
U
X
CVBS/Y
C/CbCr
C
Y
Output
Formatter
Y[9:0]
VBI
Data
Processor
Copy
Protection
Detector
C[9:0]
Host
Interface
Timing Processor
With Sync Detector
VI_1_A
VI_1_B
VI_1_C
VI_2_A
VI_2_B
VI_2_C
VI_3_A
VI_3_B
VI_3_C
VI_4_A
CVBS/
Y
CVBS/
C/Pb
CVBS/
C/Pr
CVBS/Y
CVBS/Y
Analog
Front End
Sampling
Clock
GPIO
HS/CS
VS/VBLK
FID
AVID
XTAL1 XTAL2
DATACLK
RESETB
GLCO
PWDN
SCL
SDA
YCbCr
Clamping
AGC
2 × 11-Bit
ADC
TVP5147M1
SLES140G –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
1.6 Functional Block Diagram
Figure 1-1. Functional Block Diagram
12 Introduction Copyright © 2005–2012, Texas Instruments Incorporated
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