Datasheet

Single Byte
B8S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
VBUS Write
B8S ACK E0 ACK Send Data ACK P
Multiple Bytes
B8
S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
B8S ACK E1 ACK Send Data ACK ACK PSend Data• ••
Single Byte
B8
S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
VBUS Read
B8S ACK E0 ACK ACK
Multiple Bytes
B8
S ACK E8 ACK VA0 ACK VA1 ACK VA2 ACK P
B8S ACK E1 ACK ACK NAK PRead Data•••
Read Data NAK PS B9
S B9 ACK Read Data
HOST
Processor
I
2
C
VBUS
Data
I
2
C Registers
00h
E0h
E1h
VBUS
Address
E8h
EAh
FFh
VBUS[23:0]
Line
Mode
VBUS Registers
00 0000h
FIFO
VPS
VITC
WSS
CC
80 051Ch
80 0520h
80 052Ch
80 0600h
80 0700h
90 1904h
FF FFFFh
NOTE: Examples use default I
2
C address
ACK = Acknowledge generated by the slave
NAK = No acknowledge generated by the master
TVP5147M1
SLES140G –JULY 2005–REVISED FEBRUARY 2012 www.ti.com
2.6.3 VBUS Access
The TVP5147M1 decoder has additional internal registers accessible through an indirect access to an
internal 24-bit address wide VBUS. Figure 2-17 shows the VBUS register access.
Figure 2-17. VBUS Access
32 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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