Datasheet

TVP5147M1
www.ti.com SLES140G –JULY 2005–REVISED FEBRUARY 2012
Table 2-80. Chip ID MSB Register
Subaddress 80h
Read only
7 6 5 4 3 2 1 0
CHIP ID MSB[7:0]
CHIP ID MSB[7:0]:
This register identifies the MSB of the device ID. Value = 51h
Table 2-81. Chip ID LSB Register
Subaddress 81h
Read only
7 6 5 4 3 2 1 0
CHIP ID LSB [7:0]
CHIP ID LSB [7:0]:
This register identifies the LSB of the device ID. Value = 47h
Table 2-82. RAM Version LSB Register
Subaddress 82h
Read only
7 6 5 4 3 2 1 0
RAM version LSB [7:0]
RAM version LSB [7:0]:
This register identifies the LSB of the RAM code revision number.
Example:
Patch Release = v07.02.00
ROM Version = 07h
RAM Version MSB = 02h
RAM Version LSB = 00h
Table 2-83. Color PLL Speed Control Register
Subaddress 83h
Default 09h
7 6 5 4 3 2 1 0
Reserved Speed[3:0]
Speed [3:0]:
Color PLL speed control
1001 = Faster (default)
1010 =
1011 = Slower
Other = Reserved
Table 2-84. Status Request Register
Subaddress 97h
Default 00h
7 6 5 4 3 2 1 0
Reserved Capture
Capture:
Setting a 1b in this register causes the internal processor to capture the current settings of the AGC status and the vertical line count
registers. Because this capture is not immediate, it is necessary to check for completion of the capture by reading the capture bit
repeatedly after setting it and waiting for it to be cleared by the internal processor. Once the capture bit is 0b, the AGC status and
vertical line counters (3Ch/3Dh and 9Ah/9Bh) have been updated and can be safely read in any order.
Copyright © 2005–2012, Texas Instruments Incorporated Functional Description 71
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