Datasheet
TVP5147M1
SLES140G –JULY 2005–REVISED FEBRUARY 2012
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Table 2-98. VDP Full Field Enable Register
Subaddress D9h
Default 00h
7 6 5 4 3 2 1 0
Reserved Full field enable
Full field enable:
0 = Disabled full field mode(default)
1 = Enabled full field mode
This register enables the full field mode. In this mode, all lines outside the vertical blank area and all lines in the line mode register
programmed with FFh are sliced with the definition of the VDP full field mode register at subaddress DAh. Values other than FFh in the
line mode registers allow a different slice mode for that particular line.
Table 2-99. VDP Full Field Mode Register
Subaddress DAh
Default FFh
7 6 5 4 3 2 1 0
Full field mode [7:0]
Full field mode [7:0]:
This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over
the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode. The full
field mode register has the same bit definition as line mode registers (default FFh).
Global line mode has priority over the full field mode.
Table 2-100. VBUS Data Access With No VBUS Address Increment Register
Subaddress E0h
Default 00h
7 6 5 4 3 2 1 0
VBUS data [7:0]
VBUS data [7:0]:
VBUS data register for VBUS single byte read/write transaction.
Table 2-101. VBUS Data Access With VBUS Address Increment Register
Subaddress E1h
Default 00h
7 6 5 4 3 2 1 0
VBUS data [7:0]
VBUS data [7:0]:
VBUS data register for VBUS multi-byte read/write transaction. VBUS address is auto-incremented after each data byte read/write.
Table 2-102. FIFO Read Data Register
Subaddress E2h
Read only
7 6 5 4 3 2 1 0
FIFO Read Data [7:0]
FIFO Read Data [7:0]:
This register is provided to access VBI FIFO data through the I
2
C interface. All forms of teletext data come directly from the FIFO, while
all other forms of VBI data can be programmed to come from registers or from the FIFO. If the host port is to be used to read data from
the FIFO, then bit 0 (host access enable) in the VDP FIFO output control register at subaddress C0h must be set to 1 (see Table 2-92).
78 Functional Description Copyright © 2005–2012, Texas Instruments Incorporated
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