Datasheet

TVP5147M1
www.ti.com SLES140G –JULY 2005–REVISED FEBRUARY 2012
Table 2-103. VBUS Address Register
Subaddress E8h E9h EAh
Default 00h 00h 00h
Subaddress 7 6 5 4 3 2 1 0
E8h VBUS address [7:0]
E9h VBUS address [15:8]
EAh VBUS address [23:16]
VBUS address [23:0]:
VBUS is a 24-bit wide internal bus. The user needs to program in these registers the 24-bit address of the internal register to be
accessed via host port indirect access mode.
Table 2-104. Interrupt Raw Status 0 Register
Subaddress F0h
Read only
7 6 5 4 3 2 1 0
FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line
The host Interrupt Raw Status 0 and Interrupt Raw Status 1 registers represent the interrupt status without applying mask bits.
FIFO THRS:
FIFO threshold passed, unmasked
0 = Not passed
1 = Passed
TTX:
Teletext data available unmasked
0 = Not available
1 = Available
WSS/CGMS:
WSS/CGMS data available unmasked
0 = Not available
1 = Available
VPS/Gemstar:
VPS/Gemstar data available unmasked
0 = Not available
1 = Available
VITC:
VITC data available unmasked
0 = Not available
1 = Available
CC F2:
CC field 2 data available unmasked
0 = Not available
1 = Available
CC F1:
CC field 1 data available unmasked
0 = Not available
1 = Available
Line:
Line number interrupt unmasked
0 = Not available
1 = Available
Copyright © 2005–2012, Texas Instruments Incorporated Functional Description 79
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