Datasheet

TVP5147M1
www.ti.com SLES140G –JULY 2005–REVISED FEBRUARY 2012
Table 2-108. Interrupt Mask 0 Register
Subaddress F4h
Read only
7 6 5 4 3 2 1 0
FIFO THRS TTX WSS/CGMS VPS/Gemstar VITC CC F2 CC F1 Line
The host Interrupt Mask 0 and Interrupt Mask 1 registers can be used by the external processor to mask unnecessary interrupt sources for
the Interrupt Status 0 and Interrupt Status 1 register bits, and for the external interrupt terminal. The external interrupt is generated from all
nonmasked interrupt flags.
FIFO THRS:
FIFO threshold passed mask
0 = Disabled (default)
1 = Enabled FIFO_THRES interrupt
TTX:
Teletext data available mask
0 = Disabled (default)
1 = Enabled TTX available interrupt
WSS/CGMS:
WSS/CGMS data available mask
0 = Disabled (default)
1 = Enabled WSS/CGMS available interrupt
VPS/Gemstar:
VPS/Gemstar data available mask
0 = Disabled (default)
1 = Enabled VPS/Gemstar available interrupt
VITC:
VITC data available mask
0 = Disabled (default)
1 = Enabled VITC available interrupt
CC F2:
CC field 2 data available mask
0 = Disabled (default)
1 = Enabled CC field 2 available interrupt
CC F1:
CC field 1 data available mask
0 = Disabled (default)
1 = Enabled CC field 1 available interrupt
LINE:
Line number interrupt mask
0 = Disabled (default)
1 = Enabled Line_INT interrupt
Copyright © 2005–2012, Texas Instruments Incorporated Functional Description 83
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