Datasheet

3−4
3.3.3.2 I
2
C Host Port Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Bus free time between STOP and START 1.3 µs
t
2
Setup time for a (repeated) START condition 0.6 µs
t
3
Hold time (repeated) START condition 0.6 µs
t
4
Setup time for a STOP condition 0.6 ns
t
5
Data setup time 100 ns
t
6
Data hold time 0 0.9 µs
t
7
Rise time VC1(SDA) and VC0(SCL) signal 250 ns
t
8
Fall time VC1(SDA) and VC0(SCL) signal 250 ns
C
b
Capacitive load for each bus line 400 pF
f
I2C
I
2
C clock frequency 400 kHz
VC1 (SDA)
t
1
t
6
t
7
t
2
t
8
t
3
t
4
t
6
VC0 (SCL)
Data
Stop Start Stop
t
5
Figure 3−2. I
2
C Host Port Timing