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TVP5150PBS Ultralow-Power

NTSC/PAL Video Decoder

Data Manual

Literature Number: SLES043A

May 2006

Printed on Recycled Pape

Summary of content (68 pages)

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TVP5150PBS Ultralow-Power NTSC/PAL Video Decoder Data Manual Literature Number: SLES043A May 2006 Printed on Recycled Paper
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Contents Section 1 2 3 Page TVP5150 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.1 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.
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Contents Section Page 3.22.12 3.22.13 3.22.14 3.22.15 3.22.16 3.22.17 3.22.18 3.22.19 3.22.20 3.22.21 3.22.22 3.22.23 3.22.24 3.22.25 3.22.26 3.22.27 3.22.28 3.22.29 3.22.30 3.22.31 3.22.32 3.22.33 3.22.34 3.22.35 3.22.36 3.22.37 3.22.38 3.22.39 3.22.40 3.22.41 3.22.42 3.22.43 3.22.44 3.22.45 3.22.46 3.22.47 3.22.48 3.22.49 3.22.50 3.22.51 3.22.52 3.22.53 3.22.54 3.22.55 3.22.56 3.22.57 3.22.58 3.22.59 iv SLES043A Hue Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Section 4 5 6 Page 3.22.60 Pixel Alignment Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22.61 FIFO Output Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22.62 Automatic Initialization Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3.22.63 Full Field Enable Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Figures List of Figures Figure 2−1 2−2 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 3−13 3−14 3−15 4−1 4−2 5−1 vi Page Functional Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . TVP5150 PBS-Package Terminal Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Composite Processing Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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List of Tables Table 2−1 3−1 3−2 3−3 3−4 3−5 3−6 3−7 3−8 3−9 3−10 3−11 3−12 May 2006 Page Terminal Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Data Types Supported by the VDP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Ancillary Data Format and Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .
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Features 1 TVP5150 Features D Accepts NTSC (N, 4.43), PAL (B, D, G, H, I, D D D D D D D D D D D D M, N) Video Data Supports ITU−R BT.
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Introduction 2 Introduction 2.1 Description The TVP5150 device is an ultralow-power video decoder for NTSC and PAL video signals. Available in a space saving 32-pin TQFP package, the TVP5150 device converts NTSC and PAL video signals to 8-bit ITU−R BT.656 format. Discrete syncs are also available. The optimized architecture of the TVP5150 device allows for ultralow-power consumption.
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Introduction 2.3 Trademarks • • • • 2.4 CompactPCI is a trademark of PICMG – PCI Industrial Computer Manufacturers Group, Inc. Intel is a trademark of Intel Corporation. TI and MicroStar BGA are trademarks of Texas Instruments Other trademarks are the property of their respective owners Document Conventions Throughout this data manual, several conventions are used to convey information. These conventions are listed below: 1. To identify a binary number or field, a lower case b follows the numbers.
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Introduction 2.6 Functional Block Diagram AIP1B A/D AGC LUMINANCE PROCESSING CHROMINANCE PROCESSING OUTPUT FORMATTER M U X AIP1A Y/C SEPARATION MACROVISION DETECTION YOUT[7:0] YUV 8-BIT 4:2:2 VBI / DATA SLICER SCL SDA I2C INTERFACE HOST PROCESSOR PDN SCLK SYNC PROCESSOR XTAL2 LINE AND CHROMA PLLS XTAL1 FID/GLCO VSYNC/PALI INTERQ/GPCL/VBLK HSYNC AVID Figure 2−1. Functional Block Diagram 2.
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Introduction VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 TQFP PACKAGE (TOP VIEW) 24 23 22 21 20 19 18 17 HSYNC AVID INTERQ/GPCL/VBLK PDN REFP REFM CH1_AGND CH1_AVDD 25 16 26 15 27 14 28 13 29 12 30 11 31 10 32 9 4 5 6 7 8 AIP1A AIP1B PLL_AGND PLL_AVDD XTAL1/OSC XTAL2 NSUB RESETB 1 2 3 YOUT2 YOUT3 YOUT4 YOUT5 YOUT6 YOUT7/I2CSEL IO_DVDD SCLK Figure 2−2. TVP5150 PBS-Package Terminal Diagram Table 2−1.
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Introduction Table 2−1. Terminal Functions (Continued) TERMINAL NAME NUMBER I/O DESCRIPTION Digital Section AVID 26 O Active video indicator. This signal is high during the horizontal active time of the video output on the Y and UV terminals. AVID continues to toggle during vertical blanking intervals. This terminal can be placed in a high-impedance state. DGND 19 I Digital ground DVDD 20 I Digital supply. Connect to 1.
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Functional Description 3 Functional Description 3.1 Input Multiplexers and Buffers The TVP5150 device has an analog input channel that accepts two video inputs, ac-coupled through 0.1-µF to 1-µF capacitors. The two analog input ports can be connected as follows: • • Two selectable composite video inputs or One S-video input The internal video multiplexers can be configured via I2C. The internal nodes are grounded for zero channel crosstalk.
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Functional Description An adaptive 4-line comb filter separates UV from Y based on the unique property of color phase shift from line to line. Chroma is remodulated through another quadrature modulator and subtracted from the line-delayed composite video to generate luma. This form of Y/C separation is completely complementary and thus loses no information. However, in some applications, it is desirable to limit the U/V bandwidth to avoid crosstalk. In that case, notch filters can be turned on.
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Functional Description The filter frequency plots show that both 4-line and 3-line (with filter coefficients [1,3,3,1]/8 and [1,2,1]/4) comb filters have zeros at 1/2 of the horizontal line frequency to separate the interleaved Y/C spectrum in NTSC. The 4-line comb filter has less cross-luma and cross-chroma noise due to slightly sharper filter cutoff. The 4-line comb filter with filter coefficients [1,1,1,1]/4 has three zeros at 1/4, 2/4, and 3/4 of the horizontal line frequency.
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Functional Description 10 10 0 0 −5 −5 −10 Notch1 Filter −15 −20 Notch3 Filter 5 Notch3 Filter Amplitude − dB Amplitude − dB 5 Notch2 Filter −25 −10 Notch1 Filter −15 −20 Notch2 Filter −25 No Notch Filter −30 −30 −35 No Notch Filter −35 −40 −40 0 1 2 3 4 5 6 7 0 1 2 f − Frequency − MHz Figure 3−3. Chroma Trap Filter Frequency Response, NTSC ITU−R BT.601 Sampling 3.7 3 4 5 6 7 f − Frequency − MHz Figure 3−4. Chroma Trap Filter Frequency Response, PAL ITU−R BT.
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Functional Description 3.8 Luminance Processing The luma component is derived from the composite signal by subtracting the remodulated chroma information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luma information is then fed into the peaking circuit, which enhances the high frequency components of the signal as shown in Figure 3−6. 7 Peak at f = 2.40 MHz 6 Gain = 2 Amplitude − dB 5 Gain = 1 4 3 Gain = 0.
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Functional Description Table 3−1. Data Types Supported by the VDP LINE MODE REGISTER (D0h−FCh) BITS [3:0] SAMPLING RATE (0Dh) BIT 7 0000b x x Reserved 0000b x x Reserved 0001b x x Reserved 0001b 1 WST PAL B 6 Teletext, PAL, System B, ITU−R BT.601 0010b x x Reserved 0010b 1 WST PAL C 6 Teletext, PAL, System C, ITU−R BT.601 0011b x x Reserved NAME DESCRIPTION 0011b 1 WST, NTSC B 6 Teletext, NTSC, System B, ITU−R BT.
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Functional Description 3.12 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in the ITU−R BT.656 mode. VBI data is output during the horizontal blanking period following the line from which the data was retrieved. Table 3−2 shows the header format and sequence of the ancillary data inserted into the video stream. This format is also used to store any VBI data into the FIFO. The size of FIFO is 512 bytes.
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Functional Description 3.13 Raw Video Data Output The TVP5150 device can output raw A/D video data at 2x sampling rate for external VBI slicing. This is transmitted as an ancillary data block during the active horizontal portion of the line and during vertical blanking. 3.14 Output Formatter The YUV digital output can be programmed as 8-bit 4:2:2 or 8-bit ITU−R BT.656 parallel interface standard. Table 3−3.
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Functional Description 3.15 Synchronization Signals Nondata stream embedded syncs are provided via the following signals: • • • • • • VSYNC (vertical sync) FID/VLK (field indicator or vertical lock indicator) GPCL/VBLK (general-purpose I/O or vertical blanking indicator) PALI/HLK (PAL switch indicator or horizontal lock indicator) HSYNC (horizontal sync) AVID (active video indicator) In hardware, VSYNC, FID, PALI, and VBLK are software-set and programmable to the SCLK pixel count.
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Functional Description 525-Line 525 1 2 3 4 5 6 7 8 9 10 11 20 21 22 Composite Video VSYNC FID GPCL/VBLK −←0→+ VBLK Start 262 263 −←0→+ VBLK Stop 264 265 266 267 268 269 270 271 272 273 282 283 284 Composite Video VSYNC FID GPCL/VBLK −←0→+ VBLK Start −←0→+ VBLK Stop 625-Line 310 311 312 313 314 315 316 317 318 319 320 333 334 335 336 Composite Video VSYNC FID GPCL/VBLK −←0→+ VBLK Start 622 623 624 −←0→+ VBLK Stop 625 1 2 3 4 5 6 7 20 21 22 23 Com
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Functional Description ITU−R BT.656 timing shown without embedded syncs.
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VBLK Stop Functional Description Active Video Area VBLK Start AVID Cropped Area AVID Start VSYNC AVID Stop HSYNC Figure 3−11. AVID Application 3.17 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the datastream on the rising and falling edges of AVID. These codes contain the V and F bits which also define vertical timing. F and V are software programmable and change after SAV but before EAV, so that the new value always appears on EAV first.
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Functional Description 3.18 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5150 device functions as a slave device only. Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor.
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Functional Description Step 4 I2C Write register address (master) Step 5 I2C Acknowledge (slave) Step 6 I2C Write data (master) Step 7† I2C Acknowledge (slave) Step 8 I2C Stop (master) 7 6 5 4 3 2 1 0 addr addr addr addr addr addr addr addr 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data 9 A 9 A 0 P † Repeat steps 6 and 7 until all data have been written. 3.18.2 I 2C Read Operation The read operation consists of two phases. The first phase is the address phase.
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Functional Description 0 Step 6 I2C Stop (master) P 3.18.2.2 Read Phase 2 Step 7 I2C Start (master) 0 S Step 8 I2C General address (master) 7 6 5 4 3 2 1 0 1 0 1 1 1 0 X 1 Step 9 I2C Acknowledge (slave) 9 A Step 10 I2C Read data (slave) 7 6 5 4 3 2 1 0 Data Data Data Data Data Data Data Data Step 11† I2C Not Acknowledge (master) A Step 12 I2C Stop (master) P 9 0 † Repeat steps 10 and 11 for all bytes read.
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Functional Description TVP5150 14.318-MHz or 27-MHz Crystal TVP5150 5 XTAL1 14.318-MHz or 27-MHz Clock XTAL1 R 6 XTAL2 CL1 5 XTAL2 6 CL2 NOTE: 100-kΩ resistor R is optional Figure 3−12. Reference Clock Configurations 3.20 Genlock Control (GLCO) and Real-Time Control (RTC) A Genlock control function is provided to support a standard video encoder to synchronize its internal color phase DCO for a clean video line and color lock.
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Functional Description 3.20.2 RTC Mode Figure 3−14 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is 4 times slower than the GLCO clock rate. For PLL frequency control, the upper 22 bits are used. Each frequency control bit is 2 clock cycles long. The active low reset bit occurs 6 CLKs after the transmission of the last bit of PLL frequency control.
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Functional Description Table 3−8.
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Functional Description Table 3−8.
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Functional Description 3.22.2 Address Analog Channel Controls Register 01h 7 6 5 4 Reserved 3 1 2 1 Automatic offset control 0 Automatic gain control Automatic offset control: 00 = Disabled 01 = Automatic offset enabled (default) 10 = Reserved 11 = Clamping level frozen to the previously set value Automatic gain control (AGC): 00 = Disabled (fixed gain value) 01 = AGC enabled (default) 10 = Reserved 11 = AGC frozen to the previously set value 3.22.
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Functional Description Lock status (HVLK) (configured along with register 0Fh): 0 = Terminal VSYNC/PALI outputs.
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Functional Description 3.22.6 Software Reset Register Address 05h 7 6 5 4 3 2 1 0 Reserved Reset Reset: 0 = Normal operation (default) 1 = Reset device 3.22.7 Color Killer Threshold Control Register Address 06h 7 6 Reserved 5 4 3 Automatic color killer 2 1 0 Color killer threshold Automatic color killer: 00 = Automatic mode (default) 01 = Reserved 10 = Color killer enabled, the UV terminals are forced to a zero color state.
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Functional Description Luma signal delay with respect to chroma signal in pixel clock increments (range −8 to +7 pixel clocks): 1111 = −8 pixel clocks delay 1011 = −4 pixel clocks delay 1000 = −1 pixel clocks delay 0000 = 0 pixel clocks delay (default) 0011 = 3 pixel clocks delay 0111 = 7 pixel clocks delay 3.22.
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Functional Description 3.22.12 Hue Control Register Address 0Bh 7 6 5 4 3 2 1 0 3 2 1 0 Hue control Hue control: 0111 1111 = +180 degrees 0000 0000 = 0 degrees (default) 1000 0000 = −180 degrees 3.22.13 Contrast Control Register Address 0Ch 7 6 5 4 Contrast control Contrast control: 1111 1111 = 255 (maximum contrast) 1000 0000 = 128 (default) 0000 0000 = 0 (minimum contrast) 3.22.
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Functional Description 3.22.15 Luminance Processing Control #3 Register Address 0Eh 7 6 5 4 3 2 Reserved 1 0 Luminance trap filter select Luminance filter stop band bandwidth (MHz): 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Luminance filter select [1:0] selects one of the four chroma trap filters to produce luminance signal by removing the chrominance signal from the composite video signal.
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Functional Description 3.22.17 Active Video Cropping Start Pixel MSB Address 11h 7 6 5 4 3 2 1 0 AVIDST_MSB [9:2] Active video cropping start pixel MSB [9:2], set this register first before setting register 12h. The TVP5150 device updates the AVID start values only when register 12h is written to. 3.22.
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Functional Description 3.22.21 Genlock and RTC Register Address 15h 7 6 5 4 3 Reserved 2 1 0 CDTO_SW Reserved GLCO/ RTC CDTO_LSB_Switch (CDTO_SW): 0 = CDTO_LSB is forced to 0 1 = CDTO_LSB is forced to 1 (default) GLCO/RTC: 0 = GLCO output 1 = RTC output (default) Figure 3−13 shows the timing of GLCO and Figure 3−14 shows the timing of RTC. 3.22.
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Functional Description Detailed timing information is also available in Section 3.15, Synchronization Signals. 3.22.
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Functional Description 0 = Disable 1 = Enable (default) Chrominance comb filter enable (CE): 0 = Disable 1 = Enable (default) Automatic color gain control (ACGC): 00 = ACGC enabled (default) 01 = Reserved 10 = ACGC disabled 11 = ACGC frozen to the previously set value 3.22.
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Functional Description Chrominance output bandwidth (MHz): WCF FILTER SELECT NTSC ITU−R BT.601 PAL ITU−R BT.601 00 1.2214 1.2214 01 0.8782 0.8782 10 0.7297 0.7297 11 0.4986 0.4986 00 1.4170 1.4170 01 1.0303 1.0303 10 0.8438 0.8438 11 0.5537 0.5537 0 1 3.22.
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Functional Description Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B. Bits loaded with a 1 allow the corresponding interrupt status bit to reset to 0. Bits loaded with a 0 have no effect on the interrupt status bits. 3.22.
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Functional Description 3.22.29 Interrupt Configuration Register B Address 1Eh 7 6 5 4 3 2 1 0 Reserved Interrupt polarity B Interrupt polarity B: 0 = Interrupt B is active low (default). 1 = Interrupt B is active high. Interrupt polarity B must be same as interrupt polarity A bit at bit 0 of the interrupt configuration register A at address C2h. Interrupt configuration register B is used to configure the polarity of interrupt B on the external interrupt pin.
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Functional Description 3.22.33 ROM Version Register Address 82h 7 6 5 4 3 2 1 0 2 1 0 1 0 ROM version: 0x01 for 1.0, 0x20 for 2.00 Value = 0x02 3.22.34 RAM Patch Code Version Register Address 83h 7 6 5 4 3 RAM patch code version: 0x10 for combined version 2-1, 0x20 for combined version 2-2 Value = 0x10 3.22.35 Vertical Line Count MSB Register Address 84h 7 6 5 4 3 2 Reserved Vertical line count MSB Vertical line count bits [9:8] 3.22.
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Functional Description Line alternation changed: 0 = Line alteration has not changed (default). 1 = Line alternation has changed. Color lock changed: 0 = Color lock status has not changed (default). 1 = Color lock status has changed. H/V lock changed: 0 = H/V lock status has not changed (default). 1 = H/V lock status has changed. TV/VCR changed: 0 = TV/VCR status has not changed (default). 1 = TV/VCR status has changed.
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Functional Description 0 = No lost lock since status register #1 was last read. 1 = Lost lock since status register #1 was last read. Color subcarrier lock status: 0 = Color subcarrier is not locked. 1 = Color subcarrier is locked. Vertical sync lock status: 0 = Vertical sync is not locked. 1 = Vertical sync is locked. Horizontal sync lock status: 0 = Horizontal sync is not locked. 1 = Horizontal sync is locked. TV/VCR status [TV/VCR mode is determined by counting the total number of lines/frame.
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Functional Description 3.22.41 Status Register #3 Address 8Ah 7 6 5 4 3 2 1 0 3 2 1 0 AGC gain AGC gain: 0000 0000 = −6 dB 0100 0000 = −3 dB 1000 0000 = 0 dB 1100 0000 = 3 dB 1111 1111 = 6 dB 3.22.42 Status Register #4 Address 8Bh 7 6 5 4 Subcarrier to horizontal (SCH) phase SCH (color PLL subcarrier phase at 50% of the falling edge of horizontal sync of line one of odd field; step size 360_/256): 0000 0000 = 0.00_ 0000 0001 = 1.41_ 0000 0010 = 2.81_ 1111 1110 = 357.
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Functional Description Video standard: VIDEO STANDARD [3:1] SR VIDEO STANDARD BIT 3 BIT2 BIT1 BIT 0 0 0 0 0 Reserved 0 0 0 1 (M) NTSC ITU−R BT.601 0 0 1 0 Reserved 0 0 1 1 (B, G, H, I, N) PAL ITU−R BT.601 0 1 0 0 Reserved 0 1 0 1 (M) PAL ITU−R BT.601 0 1 1 0 Reserved 0 1 1 1 (Combination-N) ITU−R BT.601 1 0 0 0 Reserved 1 0 0 1 NTSC 4.43 ITU−R BT.601 1 0 1 0 Reserved 1 0 1 1 Reserved Sampling rate (SR): 0 = Reserved 1 = ITU−R BT.601 3.22.
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Functional Description PAL ADDRESS 7 6 5 4 3 2 1 0 94h b7 b6 b5 b4 b3 b2 b1 b0 WSS field 1 byte 1 b13 b12 b11 b10 b9 b8 WSS field 1 byte 2 95h 96h b7 b6 97h BYTE b5 b4 b3 b2 b1 b0 WSS field 2 byte 1 b13 b12 b11 b10 b9 b8 WSS field 2 byte 2 98h Reserved 99h Reserved PAL: Bits 0−3 represent group 1, aspect ratio Bits 4−7 represent group 2, enhanced services Bits 8−10 represent group 3, subtitles Bits 11−13 represent group 4, others 3.22.
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Functional Description 3.22.48 VBI FIFO Read Data Register Address B0h 7 6 5 4 3 2 1 0 FIFO read data This address is provided to access VBI data in the FIFO through the host port. All forms of teletext data come directly from the FIFO, while all other forms of VBI data can be programmed to come from the registers or from the FIFO. Current status of the FIFO can be found at address C6h and the number of bytes in the FIFO is located at address C7h.
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Functional Description 3.22.
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Functional Description FIFO threshold interrupt: 0 = The amount of data in the FIFO has not yet crossed the threshold programmed at address C8h. 1 = The amount of data in the FIFO has crossed the threshold programmed at address C8h. Line interrupt: 0 = The video line number has not yet been reached. 1 = The video line number programmed in address CAh has occurred. Data interrupt: 0 = No data is available. 1 = VBI data is available either in the FIFO or in the VBI data registers. 3.22.
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Functional Description 3.22.53 Interrupt Configuration Register A Address C2h 7 6 5 4 3 Reserved 2 1 0 YUV enable (VDPOE) Interrupt A Interrupt polarity A YUV enable (VDPOE): 0 = YUV pins are high impedance. 1 = YUV pins are active if other conditions are met (default). Interrupt A (read-only): 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin. Interrupt polarity A: 0 = Interrupt A is active low (default).
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Functional Description Table 3−12.
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Functional Description 3.22.55 VDP Status Register Address C6h 7 6 5 4 3 2 1 0 FIFO full error FIFO empty TTX available CC field 1 available CC field 2 available WSS available VPS available VITC available The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically.
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Functional Description This register provides the number of words in the FIFO. 1 word equals 2 bytes. 3.22.57 FIFO Interrupt Threshold Register Address C8h 7 6 5 4 3 2 1 0 Number of words This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h). This interrupt must be enabled at address C1h. 1 word equals 2 bytes. 3.22.
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Functional Description 3.22.61 FIFO Output Control Register Address CDh 7 6 5 4 3 2 1 0 Reserved Host access enable This register is programmed to allow I2C access to the FIFO or allowing all VDP data to go out the video port. Host access enable: 0 = Output FIFO data to the video output Y[9:2] (default) 1 = Allow I2C access to the FIFO data 3.22.
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Functional Description 3.22.
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Functional Description These registers program the specific VBI standard at a specific line in the video field. Bit 7: 0 = Disable filtering of null bytes in closed caption modes 1 = Enable filtering of null bytes in closed caption modes (default) In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, then the data filter passes all data on that line. Bit 6: 0 = Send VBI data to registers only. 1 = Send VBI data to FIFO and the registers.
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Electrical Characteristics 4 Electrical Characteristics 4.1 Absolute Maximum Ratings Over Operating Free-Air Temperature Range (unless otherwise noted)† Supply voltage range: IOVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 4.5 V DVDD to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.5 V to 2.3 V PLL_AVDD to PLL_AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . −0.
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Electrical Characteristics 4.3.1 DC Electrical Characteristics TEST CONDITIONS (see Note 1) PARAMETER MIN TYP MAX UNIT IDD(IO_D) IDD(D) Digital I/O supply current Color bar input 6 mA Digital core supply current Color bar input 21 mA IDD(PLL_A) IDD(CH1_A) Analog PLL supply current Color bar input 6 mA Analog PLL supply current Color bar input 25 mA PTOT PDOWN Total power dissipation, normal mode Color bar input 113 Total power dissipation, power-down mode Color bar input 0.
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Electrical Characteristics 4.3.3 Timing 4.3.3.1 Clocks, Video Data, Sync Timing TEST CONDITIONS (see NOTE 2) PARAMETER MIN Duty cycle PCLK, SCLK t1 TYP MAX UNIT 50% See Note 3 (by design) Delay time, SCLK falling edge to digital outputs 2.8 8 TYP MAX ns NOTES: 3. CL = 15 pF 4. All outputs are 3.3 V. SCLK t1 HSYNC/VSYNC/AVID/ PALI/FID/Y[7:0] Figure 4−1. Clocks, Video Data, and Sync Timing 4.3.3.
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Application Information 5 Application Information 5.1 Application Example NOTE: X and (75 − X) is used since the maximum P−P signal allowed is 0.75V. Hence for a 140IRE signal, the signal must be divided by approximately half. Change X depending on the input signal range. C2 C1 1uF 1uF C3 C11 PDN INTERQ/GPCL AVID HSYNC 1uF 0.1uF R2 C11 AVDD IO_DVDD (75−X) R5 0.
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Mechanical Data 6 Mechanical Data The TVP5150 device is available in the 32-terminal PQFP package (PBS). The following figure shows the mechanical dimensions for the PBS package. PBS (S-PQFP-G32) PLASTIC QUAD FLATPACK 0,23 0,17 0,50 24 0,08 M 17 25 16 32 9 0,13 NOM 1 8 3,50 TYP Gage Plane 5,05 SQ 4,95 7,10 SQ 6,90 0,25 0,10 MIN 0°−ā 7° 0,70 0,40 1,05 0,95 Seating Plane 1,20 MAX 0,08 4087735/A 11/95 NOTES: A. All linear dimensions are in millimeters. B.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device TVP5150PBSR Package Package Pins Type Drawing TQFP PBS 32 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 1000 330.0 16.4 Pack Materials-Page 1 7.2 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 7.2 1.5 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5150PBSR TQFP PBS 32 1000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.