TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Ultralow-Power NTSC/PAL/SECAM Video Decoder Check for Samples: TVP5151 1 Introduction 1.1 Features 1 • Accepts NTSC (J, M, 4.43), PAL (B, D, G, H, I, M, N, Nc), and SECAM (B, D, G, K, K1, L) Video • Supports ITU-R BT.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com The TVP5151 decoder utilizes Texas Instruments patented technology for locking to weak, noisy, or unstable signals. A Genlock/real-time control (RTC) output is generated for synchronizing downstream video encoders. Complementary four-line adaptive comb filtering is available for both the luminance and chrominance data paths to reduce both cross-luminance and cross-chrominance artifacts; a chrominance trap filter is also available.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 1.4 Related Products • • • • • 1.5 TVP5150AM1 TVP5154A TVP5146M2 TVP5147M1 TVP5158 Trademarks TI and MicroStar Junior are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Gemstar is a trademark of Gemstar-TV Guide International. Other trademarks are the property of their respective owners. 1.6 Document Conventions Throughout this data manual, several conventions are used to convey information.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 1 2 3 4 www.ti.com .............................................. 1 1.1 Features .............................................. 1 1.2 Description ........................................... 1 1.3 Applications .......................................... 2 1.4 Related Products ..................................... 3 1.5 Trademarks .......................................... 3 1.6 Document Conventions .............................. 3 1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 2 Device Details 2.1 Functional Block Diagram PGA AIP1A AIP1B M U X A/D Luminance Processing Output Formatter Y/C Separation Macrovision Detection Chrominance Processing YOUT[7:0] YCbCr 8-Bit 4:2:2 VBI Data Processor (VDP) SCL SDA Host Interface Embedded Processor PDN SCLK Horizontal and Color PLLs XTAL2 Timing Processor XTAL1/OSC FID/GLCO VSYNC/PALI INTREQ/GPCL/VBLK HSYNC AVID/CLK_IN Figure 2-1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 2.2 www.ti.com Terminal Assignments The TVP5151 video decoder is packaged in a 48-terminal PBGA package or a 32-terminal TQFP package. Figure 2-2 shows the terminal diagrams for both packages. Table 2-1 gives a description of the terminals.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 2.3 Terminal Functions Table 2-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION ZQC PBS AGND E1 7 G Substrate. Connect to analog ground. AIP1A A1 1 I Analog input. Connect to the video analog input via 0.1-µF capacitor. The maximum input range is 0-0.75 VPP, and may require an attenuator to reduce the input amplitude to the desired level. If not used, connect to AGND via a 0.1-µF capacitor (see Figure 6-1).
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 2-1. Terminal Functions (continued) TERMINAL NAME NO. ZQC I/O DESCRIPTION PBS This terminal has three functions selectable by bit 7 of I2C register 03h and bit 1 of I2C register 0Fh: • INTREQ: Interrupt request output • GPCL: General-purpose control logic output. In this mode, the state of terminal 27 is directly programmed via I2C. • VBLK: Vertical blanking output.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3 Functional Description 3.1 Analog Front End The TVP5151 decoder has an analog input channel that accepts two video inputs that are ac-coupled. The decoder supports a maximum input voltage range of 0.75 V; therefore, an attenuation of one-half is needed for most input signals with a peak-to-peak variation of 1.5 V. The nominal parallel termination before the input to the device is recommended to be 75 Ω.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Gain Factor Peak Detector Bandpass X Peaking Composite Delay Line Delay + Delay Y Y Quadrature Modulation Brightness Saturation Adjust SECAM Luminance Cr Notch Filter Cb Composite SECAM Color Demodulation Cb Composite Quadrature Modulation Cr Cr Notch Filter Color LPF ↓ 2 Burst Accumulator (Cb) Cb 4-Line Adaptive Comb Filter Color LPF ↓ 2 LP Filter LP Filter Delay Delay Burst Accumulator (Cr) Figure 3-1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Figure 3-2. Chrominance Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling 3.4 Figure 3-3. Chrominance Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling Color Low-Pass Filter In some applications, it is desirable to limit the Cb/Cr bandwidth to avoid crosstalk. This is especially true in case of video signals that have asymmetrical Cb/Cr sidebands. The color LP filters provided limit the bandwidth of the Cb/Cr signals.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 3.5 www.ti.com Luminance Processing The luminance component is derived from the composite signal by subtracting the remodulated chrominance information. A line delay exists in this path to compensate for the line delay in the adaptive comb filter in the color processing chain. The luminance information is then fed into the peaking circuit, which enhances the high frequency components of the signal, thus improving sharpness. 3.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com At power-up the host interface is required to program the VDP-configuration RAM (VDP-CRAM) contents with the lookup table (see Section 3.21.64). This is done through port address C3h. Each read from or write to this address auto increments an internal counter to the next RAM location.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 IDID1: www.ti.com Bit 0/1 = Transaction video line number [9:8] Bit 2 = Match 2 flag Bit 3 = Match 1 flag Bit 4 = 1 if an error was detected in the EDC block; 0 if not CS: Sum of D0–D7 of DID through last data byte. Fill byte: Fill bytes make a multiple of 4 bytes from byte 0 to last fill byte. 3.10 Raw Video Data Output The TVP5151 decoder can output raw A/D video data at 2x sampling rate for external VBI slicing.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com ITU-R BT.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 VBLK Stop www.ti.com Active Video Area VBLK Start AVID Cropped Area AVID Stop VSYNC AVID Start HSYNC Figure 3-7. AVID Application 3.14 Embedded Syncs Standards with embedded syncs insert SAV and EAV codes into the datastream at the beginning and end of horizontal blanking. These codes contain the V and F bits that also define vertical timing. F and V change on EAV. Table 3-4 gives the format of the SAV and EAV codes.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used for slave address selection. Although the I2C system can be multimastered, the TVP5151 decoder functions only as a slave device.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.1 I2C Write Operation Data transfers occur utilizing the following illustrated formats. An I2C master initiates a write operation to the TVP5151 decoder by generating a start condition (S) followed by the TVP5151 I2C slave address (see the following illustration), in MSB first bit order, followed by a 0 to indicate a write cycle.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.2.1 Read Phase 1 Step 1 0 I2C Start (master) S Step 2 7 6 5 4 3 2 1 0 I2C slave address (master) 1 0 1 1 1 0 X 0 Step 3 9 2 I C Acknowledge (slave) Step 4 I2C Write register address (master) A 7 6 5 4 3 2 1 0 Addr Addr Addr Addr Addr Addr Addr Addr Step 5 9 I2C Acknowledge (slave) A Step 6 0 2 I C Stop (master) P 3.15.2.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.15.2.3 I2C Timing Requirements The TVP5151 decoder requires delays in the I2C accesses to accommodate its internal processor's timing. In accordance with I2C specifications, the TVP5151 decoder holds the I2C clock line (SCL) low to indicate the wait period to the I2C master. If the I2C master is not designed to check for the I2C clock line held-low condition, then the maximum delays must always be inserted where required.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.17 Genlock Control (GLCO) and RTC A Genlock control function is provided to support a standard video encoder to synchronize its internal color oscillator for properly reproduced color with unstable timebase sources such as VCRs. The frequency control word of the internal color subcarrier digitally tuned oscillator (DTO) and the subcarrier phase reset bit are transmitted via terminal 23 (GLCO).
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.17.2 RTC Mode Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the last bit of PLL frequency control.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are high-impedance until the chip is initialized and the outputs are activated. PLL_AVDD DVDD IO_DVDD t1 Normal Operation RESETB Reset t2 PDN t3 SDA Data SCL Figure 3-11. Power-On Reset Timing Table 3-9. Power-On Reset Timing NO.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.19 Reset Sequence Table 3-10 shows the reset sequence of the TVP5151 pins status during reset time and immediately after reset time. Table 3-10.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.20 Internal Control Registers The TVP5151 decoder is initialized and controlled by a set of internal registers that set all device operating parameters. Communication between the external controller and the TVP5151 decoder is through I2C. Table 3-11 shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined registers must be written with zeros, unless otherwise noted.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 3-11.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Table 3-11.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21 Register Definitions 3.21.1 Video Input Source Selection #1 Register Address Default 00h 00h 7 6 5 4 3 Black output Reserved 2 Reserved 1 Channel 1 source selection 0 S-video selection Channel 1 source selection 0 = AIP1A selected (default) 1 = AIP1B selected Table 3-12.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Vertical blanking on/off 0 = Vertical blanking (VBLK) off (default) 1 = Vertical blanking (VBLK) on Clock output enable 0 = SCLK output is high impedance (default) 1 = SCLK output is enabled Note: To achieve lowest power consumption, outputs placed in the high-impedance state should not be left floating. A 10-kΩ pulldown resistor is recommended if not driven externally.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.5 Autoswitch Mask Register Address Default 04h DCh 7 6 Reserved 5 SEC_OFF 4 N4.43_OFF 3 PALN_OFF 2 PALM_OFF 1 0 Reserved N4.43_OFF 0 = NTSC4.43 is unmasked from the autoswitch process. Autoswitch does switch to NTSC4.43. 1 = NTSC4.43 is masked from the autoswitch process. Autoswitch does not switch to NTSC4.43 (default). PALN_OFF 0 = PAL-N is unmasked from the autoswitch process. Autoswitch does switch to PAL-N.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.8 Luminance Processing Control #1 Register Address Default 7 2× luminance output enable 07h 60h 6 Pedestal not present 5 Disable raw header 4 Luminance bypass enabled during vertical blanking 3 2 1 0 Luminance signal delay with respect to chrominance signal 2× luminance output enable 0 = Output depends on bit 4, luminance bypass enabled during vertical blanking (default). 1 = Outputs 2x luminance samples during the entire frame.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.9 Luminance Processing Control #2 Register Address Default 7 Reserved 08h 00h 6 Luminance filter select 5 4 3 Reserved 2 1 0 Mac AGC control 2 1 Peaking gain Luminance filter select 0 = Luminance comb filter enabled (default) 1 = Luminance chrominance trap filter enabled Peaking gain (sharpness) 00 = 0 (default) 01 = 0.5 10 = 1 11 = 2 Information on peaking frequency: ITU-R BT.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.11 Color Saturation Control Register Address Default 0Ah 80h 7 6 5 4 3 2 1 0 Saturation[7:0] Saturation[7:0]: This register works for CVBS and S-Video chrominance.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.13 Outputs and Data Rates Select Register Address Default 7 Reserved 0Dh 47h 6 YCbCr output code range 5 CbCr code format 4 3 YCbCr data path bypass 2 1 YCbCr output format 0 YCbCr output code range 0 = ITU-R BT.601 coding range (Y ranges from 16 to 235.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.14 Luminance Processing Control #3 Register Address Default 7 0Eh 00h 6 5 4 3 2 Reserved 1 0 Luminance trap filter select Luminance filter stop band bandwidth (MHz) 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Luminance filter select [1:0] selects one of the four chrominance trap (notch) filters to produce luminance signal by removing the chrominance signal from the composite video signal.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.17 Active Video Cropping Start Pixel LSB Register Address Default 12h 00h 7 6 5 Reserved 4 3 2 AVID active 1 0 AVID start pixel LSB [1:0] AVID active 0 = AVID out active in VBLK (default) 1 = AVID out inactive in VBLK Active video cropping start pixel LSB [1:0]: The TVP5151 decoder updates the AVID start values only when this register is written to.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.20 Genlock and RTC Register Address Default 15h 01h 7 6 5 Reserved 4 3 Reserved F/V bit control 2 1 GLCO/RTC 0 F/V bit control BIT 5 0 BIT 4 NUMBER OF LINES 0 0 1 1 0 1 1 F BIT V BIT Standard ITU-R BT.656 ITU-R BT.656 Nonstandard even Force to 1 Switch at field boundary Nonstandard odd Toggles Switch at field boundary Standard ITU-R BT.656 ITU-R BT.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com BT.656 EAV Code U Y V Y F F YOUT[7:0] 0 0 0 0 X Y BT.656 SAV Code 8 0 1 0 8 0 1 0 F F 0 0 0 0 X Y U Y HSYNC AVID 128 SCLK Start of Digital Line Start of Digital Active Line Nhbhs Nhb Figure 3-13. Horizontal Sync Table 3-14. Clock Delays (SCLKs) STANDARD Nhbhs Nhb NTSC 28 272 PAL 32 284 SECAM 32 284 Detailed timing information is also available in Section 3.12. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.25 Chrominance Control #2 Register Address Default 7 1Bh 14h 6 5 Reserved 4 3 2 WCF 1 0 Chrominance filter select Wideband chrominance filter (WCF) 0 = Disable 1 = Enable (default) Chrominance low pass filter select 00 = No notch (default) 01 = Notch 1 10 = Notch 2 11 = Notch 3 Chrominance output bandwidth (MHz) WCF 0 1 FILTER SELECT NTSC/PAL/SECAM ITU-R BT.601 00 1.2214 01 0.8782 10 0.7297 11 0.4986 00 1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.26 Interrupt Reset Register B Address Default 7 Software initialization reset 1Ch 00h 6 Macrovision detect changed reset 5 Reserved 4 Field rate changed reset 3 Line alternation changed reset 2 Color lock changed reset 1 H/V lock changed reset 0 TV/VCR changed reset Interrupt reset register B is used by the external processor to reset the interrupt status bits in interrupt status register B.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.27 Interrupt Enable Register B Address Default 7 Software initialization occurred 1Dh 00h 6 Macrovision detect changed 5 Reserved 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed Interrupt enable register B is used by the external processor to mask unnecessary interrupt sources for interrupt B.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.28 Interrupt Configuration Register B Address Default 1Eh 00h 7 6 5 4 Reserved 3 2 1 0 Interrupt polarity B Interrupt polarity B 0 = Interrupt B is active low (default). 1 = Interrupt B is active high. Interrupt polarity B must be the same as interrupt polarity A of Interrupt Configuration Register A at Address C2h.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.31 Indirect Register Read/Write Strobe Address Default 24h 00h 7 6 5 4 3 2 1 0 R/W[7:0] This register selects the most significant bits of the indirect register address and performs either an indirect read or write operation. Data will be written from are read to Indirect Register Data registers 21h-22h.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.33 Cb Gain Factor Register Address 2Ch 7 6 5 4 3 2 1 0 Cb gain factor This is a read-only register that provides the gain applied to the Cb in the YCbCr data stream. 3.21.34 Cr Gain Factor Register Address 2Dh 7 6 5 4 3 2 1 0 Cr gain factor This is a read-only register that provides the gain applied to the Cr in the YCbCr data stream. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.38 Patch Write Address Address Default 7Eh 00h 7 6 5 4 3 2 1 0 R/W[7:0] This register is used for downloading firmware patch code. Please refer to the patch load application note for more detail. This register must not be written to or read from during normal operation. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.42 ROM Version Register Address Default 82h 04h 7 6 5 4 3 ROM version [7:0] 2 1 0 1 0 ROM Version [7:0]: This register identifies the ROM code revision number. 3.21.43 RAM Version Register Address Default 83h 00h 7 6 5 4 3 RAM version [7:0] 2 RAM Version [7:0]: This register identifies the RAM code revision number. Example: Patch Release = v01.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.46 Interrupt Status Register B Address 7 Software initialization 86h 6 Macrovision detect changed 5 Reserved 4 Field rate changed 3 Line alternation changed 2 Color lock changed 1 H/V lock changed 0 TV/VCR changed Software initialization 0 = Software initialization is not ready. 1 = Software initialization is ready. Macrovision detect changed 0 = Macrovision detect status has not changed.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.47 Interrupt Active Register B Address 87h 7 6 5 4 Reserved 3 2 1 0 Interrupt B Interrupt B 0 = Interrupt B is not active on the external terminal (default). 1 = Interrupt B is active on the external terminal. The interrupt active register B is polled by the external processor to determine if interrupt B is active. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.49 Status Register #2 Address 7 Reserved 89h 6 Weak signal detection 5 PAL switch polarity 4 Field sequence status 3 AGC and offset frozen status 2 1 Macrovision detection 0 Weak signal detection 0 = No weak signal 1 = Weak signal mode PAL switch polarity of first line of odd field 0 = PAL switch is 0. 1 = PAL switch is 1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.52 Status Register #5 Address 8Ch 7 Autoswitch mode 6 5 Reserved 4 3 2 Video standard 1 0 Sampling rate (SR) This register contains information about the detected video standard at which the device is currently operating. When autoswitch code is running, this register must be tested to determine which video standard has been detected.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.54 Closed Caption Data Registers Address 90h–93h Address 90h 91h 92h 93h 7 6 5 4 Closed Closed Closed Closed 3 caption field 1 byte caption field 1 byte caption field 2 byte caption field 2 byte 2 1 0 1 2 1 2 These registers contain the closed caption data arranged in bytes per field. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.56 VPS Data Registers Address 9Ah–A6h Address 9Ah 9Bh 9Ch 9Dh 9Eh 9Fh A0h A1h A2h A3h A4h A5h A6h 7 6 5 4 3 2 1 0 VPS byte 1 VPS byte 2 VPS byte 3 VPS byte 4 VPS byte 5 VPS byte 6 VPS byte 7 VPS byte 8 VPS byte 9 VPS byte 10 VPS byte 11 VPS byte 12 VPS byte 13 These registers contain the entire VPS data line except the clock run-in code and the start code. 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.61 Interrupt Status Register A Address Default 7 Lock state interrupt C0h 00h 6 Lock interrupt 5 4 Reserved 3 2 FIFO threshold interrupt 1 Line interrupt 0 Data interrupt The interrupt status register A can be polled by the host processor to determine the source of an interrupt. After an interrupt condition is set it can be reset by writing to this register with a 1 in the appropriate bit(s).
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.62 Interrupt Enable Register A Address Default 7 Reserved C1h 00h 6 Lock interrupt enable 5 4 Reserved 3 2 FIFO threshold interrupt enable 1 Line interrupt enable 0 Data interrupt enable The interrupt enable register A is used by the host processor to mask unnecessary interrupt sources. Bits loaded with a 1 allow the corresponding interrupt condition to generate an interrupt on the external pin.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.63 Interrupt Configuration Register A Address Default C2h 04h 7 6 5 Reserved 4 3 2 YCbCr enable (VDPOE) 1 Interrupt A 0 Interrupt polarity A YCbCr enable (VDPOE) 0 = YCbCr pins are high impedance. 1 = YCbCr pins are active if other conditions are met (default) (see Table 3-13). Interrupt A (read only) 0 = Interrupt A is not active on the external pin (default). 1 = Interrupt A is active on the external pin.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com The suggested RAM contents are shown in Table 3-16. All values are hexadecimal. Table 3-16.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.65 VDP Status Register Address 7 FIFO full error C6h 6 FIFO empty 5 TTX available 4 CC field 1 available 3 CC field 2 available 2 WSS available 1 VPS available 0 VITC available The VDP status register indicates whether data is available in either the FIFO or data registers, and status information about the FIFO. Reading data from the corresponding register does not clear the status flags automatically.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.66 FIFO Word Count Register Address C7h 7 6 5 4 3 Number of words 2 1 0 1 0 This register provides the number of words in the FIFO. One word equals two bytes. 3.21.67 FIFO Interrupt Threshold Register Address Default C8h 80h 7 6 5 4 3 Number of words 2 This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value (default 80h).
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.70 Pixel Alignment Registers Address Default CBh 4Eh Address CBh CCh CCh 00h 7 6 5 4 3 Switch pixel [7:0] 2 1 Reserved 0 Switch pixel [9:8] These registers form a 10-bit horizontal pixel position from the falling edge of sync, where the VDP controller initiates the program from one line standard to the next line standard; for example, the previous line of teletext to the next line of closed caption.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 3.21.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com Bit 7 0 = Disable filtering of null bytes in closed caption modes 1 = Enable filtering of null bytes in closed caption modes (default) In teletext modes, bit 7 enables the data filter function for that particular line. If it is set to 0, the data filter passes all data on that line. Bit 6 0 = Send VBI data to registers only 1 = Send VBI data to FIFO and the registers. Teletext data only goes to FIFO (default).
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 4 Electrical Specifications Absolute Maximum Ratings (1) 4.1 over operating free-air temperature range (unless otherwise noted) Supply voltage range IO_DVDD to DGND –0.5 V to 4.5 V DVDD to DGND –0.5 V to 2.3 V PLL_AVDD to PLL_AGND –0.5 V to 2.3 V CH_AVDD to CH_AGND –0.5 V to 2.3 V Digital input voltage range, VI to DGND –0.5 V to 4.5 V Input voltage range, XTAL1 to PLL_GND –0.5 V to 2.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 4.4 www.ti.com Electrical Characteristics Typical supply voltages: DVDD = 1.8 V, PLL_AVDD = 1.8 V, CH_AVDD = 1.8 V, IO_DVDD = 3.3 V, For minimum/maximum values: TA = 0°C to 70°C for commercial or TA = –40°C to 85°C for industrial, For typical values: TA = 25°C (unless otherwise noted) 4.5 DC Electrical Characteristics TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT IDD(IO_D) 3.3-V I/O digital supply current 100% color bar input 6.9 7.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 4.7 Clocks, Video Data, Sync Timing TEST CONDITIONS (1) PARAMETER Duty cycle, SCLK MIN TYP MAX 47 50 53 t1 SCLK high time ≥90% 18.5 t2 SCLK low time ≤10% 18.5 t3 SCLK fall time 90% to 10% t4 SCLK rise time 10% to 90% t5 Propagation delay time (1) UNIT % ns ns 3 5 ns 5 ns 8 ns Measured with 22-Ω series termination resistors and 10-pF load.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com I2C Host Interface Timing (1) 4.8 NO. PARAMETER MIN TYP MAX UNIT µs t1 Bus free time between STOP and START 1.3 t2 Data Hold time t3 Data Setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 ns t6 Hold time (repeated) START condition 0.6 t7 Rise time SDA and SCL signal 250 0 µs 0.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 5 Example Register Settings The following example register settings are provided only as a reference. These settings, given the assumed input connector, video format, and output format, set up the TVP5151 decoder and provide video output. Example register settings for other features and the VBI data processor are not provided here. 5.1 5.1.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 5.2 5.2.1 www.ti.com Example 2 Assumptions Device: TVP5151 Input connector: S-video (AIP1A (luminance), AIP1B (chrominance)) Video Format: NTSC (M, 4.43), PAL (B, G, H, I, M, N, Nc) or SECAM (B, D, G, K1, L) Output format: 8-bit 4:2:2 YCbCr with discrete sync outputs 5.2.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 6 Application Information 6.1 Application Example IO_DVDD C2 1 µF C1 1 µF 10 kW See Note I C3 1 µF C4 0.1 µF R1 CH1_IN 0.1 µF AAF PDN INTREQ/GPCL/VBLK AVID HSYNC AVDD 10 kW See Note H PDN INTREQ/GPCL/VBLK AVID HSYNC IO_DVDD AVDD R6 37.4 Ω TVP5151 VSYNC/PALI FID/GLCO SDA SCL DVDD DGND YOUT0 YOUT1 S1 2 R3 2.2 kW R4 2.2 kW 24 23 22 21 20 19 18 17 VSYNC/PALI FID/GLCO SDA SCL VSYNC/PALI FID/GLCO DVDD C7 0.
TVP5151 SLES241E – SEPTEMBER 2009 – REVISED OCTOBER 2011 www.ti.com 7 Revision History Table 7-1. Revision History REVISION SLES241 COMMENTS Initial release Section 1.4, Related Products added Section 1.5, Trademarks modified Section 3.16, Figure 3-8 changed to depict various clocking options. Changed crystal parallel resistor recommendation. SLES241A Section 3.21.10, Luminance Brightness description modified Section 3.21.11, Chrominance Saturation description modified Section 3.21.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE OPTION ADDENDUM www.ti.com 31-May-2013 (3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVP5151IPBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.0 Q2 TVP5151PBSR TQFP PBS 32 1000 330.0 16.4 7.2 7.2 1.5 12.0 16.
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5151IPBSR TQFP PBS 32 1000 367.0 367.0 38.0 TVP5151PBSR TQFP PBS 32 1000 367.0 367.0 38.
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