Datasheet

TVP5151

SLES241E–SEPTEMBER 2009–REVISED OCTOBER 2011

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3.15 I

C Host Interface

The I

C standard consists of two signals, serial input/output data line (SDA) and input/output clock line

(SCL), which carry information between the devices connected to the bus. A third signal (I2CSEL) is used

for slave address selection. Although the I

C system can be multimastered, the TVP5151 decoder

functions only as a slave device.

Both SDA and SCL must be connected to a positive supply voltage via a pullup resistor. When the bus is

free, both lines are high. The slave address select terminal (I2CSEL) enables the use of two TVP5151

decoders tied to the same I

C bus. At power up, the status of the I2CSEL is polled. Depending on the

write and read addresses to be used for the TVP5151 decoder, it can either be pulled low or high through

a resistor. This terminal is multiplexed with YOUT7 and hence must not be tied directly to ground or

IO_DVDD. Table 3-6 summarizes the terminal functions of the I

C-mode host interface.

Table 3-5. Write Address

Selection

I2CSEL WRITE ADDRESS

0 B8h

1 BAh

Table 3-6. I

C Terminal Description

SIGNAL TYPE DESCRIPTION

I2CSEL (YOUT7) I Slave address selection

SCL I/O (open drain) Input/output clock line

SDA I/O (open drain) Input/output data line

Data transfer rate on the bus is up to 400 kbit/s. The number of interfaces connected to the bus is

dependent on the bus capacitance limit of 400 pF. The data on the SDA line must be stable during the

high period of the SCL except for start and stop conditions. The high or low state of the data line can only

change with the clock signal on the SCL line being low. A high-to-low transition on the SDA line while the

SCL is high indicates an I

C start condition. A low-to-high transition on the SDA line while the SCL is high

indicates an I

C stop condition.

Every byte placed on the SDA must be eight bits long. The number of bytes which can be transferred is

unrestricted. Each byte must be followed by an acknowledge bit. The acknowledge-related clock pulse is

generated by the I

C master.

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