Datasheet

RTC

16 CLK

21 0

128 CLK

22-Bit f Frequency Control

Start

Bit

Reset

Bit

2 CLK

1 CLK

2 CLK

3 CLK

1 CLK

PAL

Switch

44 CLK

TVP5151

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SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011

3.17.2 RTC Mode

Figure 3-10 shows the timing diagram of the RTC mode. Clock rate for the RTC mode is four times slower

than the GLCO clock rate. For Color PLL frequency control, the upper 22 bits are used. Each frequency

control bit is two clock cycles long. The active-low reset bit occurs six CLKs after the transmission of the

last bit of PLL frequency control.

Figure 3-10. RTC Timing

3.18 Reset and Power Down

The RESETB and PDN terminals work together to put the TVP5151 decoder into one of the two modes.

Table 3-8 shows the configuration.

After power-up, the device is in an unknown state with its outputs undefined, until it receives a RESETB

signal as depicted in Figure 3-11. After RESETB is released, outputs SCLK and YOUT0 to YOUT7 are in

high-impedance state until TVP5151 is initialized and the outputs are activated.

NOTE

C SCL and SDA signals must not change state until the TVP5151 reset sequence has been

completed.

Table 3-8. Reset and Power-Down Modes

PDN RESETB CONFIGURATION

0 0 Reserved (unknown state)

0 1 Powers down the decoder

1 0 Resets the decoder

1 1 Normal operation

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