Datasheet

TVP5151

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SLES241E–SEPTEMBER 2009– REVISED OCTOBER 2011

3.19 Reset Sequence

Table 3-10 shows the reset sequence of the TVP5151 pins status during reset time and immediately after

reset time.

Table 3-10. Reset Sequence

IMMEDIATELY AFTER

PIN DESCRIPTION DURING RESETB

RESETB

FID/GLCO, HSYNC, INTREQ/GPCL/VBLK, SCLK, VSYNC/PALI, YOUT[6:0] High-impedance High-impedance

AIP1A, AIP1B, AVID/CLK_IN, RESETB, PDN, SDA, SCL, XTAL1/OSC Input Input

XTAL2 Output Output

YOUT7/I2CSEL Input High-impedance

TVP5151 is pin compatible with TVP5150/A/AM1, and the following differences should be considered

when an upgrade is planned.

• IO_DVDD supply can be any voltage from 1.8 V to 3.3 V.

• AVID/CLK_IN is input during RESETB. If this input is used as the clock source, XTAL1/OSC pin must

be grounded.

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