Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsTVP5158IPNP

TVP5158, TVP5157, TVP5156

Four-Channel NTSC/PAL Video Decoders

With Independent Scalers, Noise Reduction, Auto

Contrast, and Flexible Output Formatter for Security and

Summary of content (109 pages)

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TVP5158, TVP5157, TVP5156 Four-Channel NTSC/PAL Video Decoders With Independent Scalers, Noise Reduction, Auto Contrast, and Flexible Output Formatter for Security and Other Multi-Channel Video Applications Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Contents 1 Introduction 1.1 1.2 1.3 1.4 1.5 1.6 1.7 1.8 2 ....................................................................................................... 12 ....................................................................................................................... 12 Functional Description ....................................................................................................... 15 3.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 ................................................................................................................ 41 ................................................................................................... 42 4.1 Overview .................................................................................................................... 42 4.2 Register Definitions ......................................................
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com List of Figures 1-1 Functional Block Diagram ....................................................................................................... 11 3-1 Video Analog Processing and ADC Block Diagram ......................................................................... 15 3-2 Anti-Aliasing Filter Frequency Response 3-3 Composite Processor Block Diagram................................................................
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 List of Tables 1-1 Device Options ..................................................................................................................... 9 2-1 Terminal Functions 3-1 3-2 3-3 3-4 3-5 3-6 3-7 3-8 3-9 3-10 3-11 3-12 3-13 3-14 3-15 3-16 3-17 3-18 3-19 4-1 4-2 4-3 4-4 4-5 4-6 4-7 4-8 4-9 4-10 4-11 4-12 4-13 4-14 4-15 4-16 4-17 4-18 4-19 4-20 4-21 4-22 4-23 4-24 4-25 4-26 ..........................................
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com .................................................................................................................. ................................................................................................................ Luma ALC Freeze Upper Threshold .......................................................................................... Chroma ALC Freeze Upper Threshold ..............................................
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 ....................................................................................................... ............................................................................................................... Audio Sample Rate Control .................................................................................................... Analog Audio Gain Control 1 ............................................................
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Four-Channel NTSC/PAL Video Decoders Check for Samples: TVP5158, TVP5157, TVP5156 1 Introduction 1.1 Features 1234 • Common Device Features (TVP5158, TVP5157, and TVP5156) – Four separate video decoder channels having the following features for each channel • Accepts NTSC (J, M, 4.
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TVP5158, TVP5157, TVP5156 www.ti.com 1.2 • • • • SLES243G – JULY 2009 – REVISED APRIL 2013 Applications Security and surveillance digital video recorders or servers and PCI products Automotive infotainment video hub Large format video wall displays Game systems 1.3 Description The TVP5158, TVP5157, and TVP5156 devices are 4-channel high-quality NTSC/PAL video decoders that digitize and decode all popular base-band analog video formats into digital video output.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 1.5 www.ti.com Trademarks DaVinci, PowerPAD are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation. Other trademarks are the property of their respective owners. 1.6 Document Conventions Throughout this data manual, several conventions are used to convey information. These conventions are as follows: • To identify a binary number or field, a lower case b follows the numbers.
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TVP5158, TVP5157, TVP5156 www.ti.com 1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 2 Terminal Assignments 2.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 2-1. Terminal Functions TERMINAL NAME NO. I/O DESCRIPTION Analog Section VIN_1_P 108 I Analog video input for ADC channel 1. VIN_1_N 109 I Common-mode reference input for ADC channel 1. VIN_2_P 112 I Analog video input for ADC channel 2. VIN_2_N 113 I Common-mode reference input for ADC channel 2. VIN_3_P 121 I Analog video input for ADC channel 3.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 2-1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION DVO_B_[7:0] 53, 54, 56, 57, 59, 60, 62, 63 O Digital video output data bus. DVO_C_[7:0] 36, 37, 39, 40, 42, 43, 45, 46 I/O Digital video output data bus. In cascade mode, all pins operate as input from another TVP5158 device. DVO_D_[7:0] 21, 22, 24, 25, 27, 28, 30, 31 I/O Digital video output data bus.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 3 Functional Description 3.1 Analog Video Processing and A/D Converters Each video decoder accepts one composite video input and performs video clamping, anti-aliasing filtering, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal. Figure 3-1 shows the video analog processing and ADC block diagram.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 3.1.2 www.ti.com Analog Video Input Clamping An internal clamping circuit provides dc restoration for all four analog composite video inputs. The dc restoration circuit (sync-tip clamp) restores sync-tip level of the ac-coupled composite video signal to a fixed dc level near the bottom of the A/D converter range. 3.1.3 A/D Converter All ADCs have a resolution of 10 bits and can operate at 27 MSPS.
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TVP5158, TVP5157, TVP5156 www.ti.com CVBS SLES243G – JULY 2009 – REVISED APRIL 2013 Line Delay Delay Peaking Y NTSC/PAL Remodulation Y Contrast Notch Notch Filter Filter Brightness Saturation Adjust Cr Color LPF 2 Cb Burst Accumulator (U) 5 Line Adaptive CVBS NTSC/PAL Demodulation Color LPF 2 Burst Accumulator (V) Comb Filter Notch Filter Delay Notch Filter Delay U V Figure 3-3. Composite Processor Block Diagram 3.2.3.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Figure 3-4. Color Low-Pass Filter Frequency Response Figure 3-5. Color Low-Pass Filter with Filter Characteristics, NTSC/PAL ITU-R BT.601 Sampling 3.2.3.2 Y/C Separation Y/C separation can be done using adaptive 5-line (5-H delay) comb filters or a chroma trap filter. The comb filter can be selectively bypassed in the luma or chroma path.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Figure 3-6. Chroma Trap Filter Frequency Response, NTSC ITU-R BT.601 Sampling Figure 3-7. Chroma Trap Filter Frequency Response, PAL ITU-R BT.601 Sampling 3.2.4 Luminance Processing The digitized composite video signal passes through either a luminance comb filter or a chroma trap filter, either of which removes chrominance information from the composite signal to generate a luminance signal.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Figure 3-9. Peaking Filter Response, NTSC/PAL ITU-R BT.601 Sampling 3.3 AVID Cropping AVID or active video cropping provides a means to decrease the amount of video data output. This is accomplished by horizontally blanking a number of AVID pulses and by vertically blanking a number of lines per frame. Horizontal cropping can be enabled/disabled using bit-6 of address B1h.
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TVP5158, TVP5157, TVP5156 www.ti.com 3.5 SLES243G – JULY 2009 – REVISED APRIL 2013 Scaler Each video decoder has an independent horizontal and vertical scaler, which supports D1 to half-D1 or CIF conversion. Table 3-2 gives the details of video resolution including un-cropped and cropped. Table 33 shows the video resolutions converted by the scaler. Table 3-2.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 3.8 www.ti.com Output Formatter The output formatter is responsible for generating the output digital video stream. Table 3-4 provides a summary of line frequencies, data rates, and pixel counts for different input standards. TVP5158 supports non-interleaved output mode, pixel-interleaved output mode and line-interleaved output mode.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 3-6. Output Ports Configuration for Pixel-Interleaved Mode Video Output Format Cascade Stage I2C Address: B0h 2-Ch D1 n/a 4-Ch D1 n/a 4-Ch Half-D1 4-Ch CIF 3.8.2.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com In 4-Ch pixel-interleaved mode, TVP5158 also supports Half-D1 and CIF format data multiplexed at 54 MHz. The output DVO_A is used in this mode. The output clock OCLK_P is synchronized with all four channels data. 3.8.2.
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TVP5158, TVP5157, TVP5156 www.ti.com 3.8.3 SLES243G – JULY 2009 – REVISED APRIL 2013 Line-Interleaved Mode Support (TVP5158 only) The TVP5158 supports 2-Ch, 4-Ch, and 8-Ch line-interleaved modes. In the line-interleaved mode, the video channels are multiplexed together on a line-by-line basis. Compared to the pixel-interleaved mode, the line-interleaved mode significantly reduces the code complexity and MIPS consumption of the backend processor.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 3.8.3.2 www.ti.com 4-Ch Line-Interleaved Mode In 4-Ch line-interleaved mode, the video output data from all 4 channels is multiplexed together on a line basis. The output resolution of video data can be D1, Half-D1 or CIF. For D1 and Half-D1 output resolutions, the video output port can be configured to support 8-bit BT.656 or 16-Bit YCbCr 4:2:2 data with embedded sync. Port DVO_A is used for 8-bit output.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 VIN_1 VIN_2 VIN_3 VIN_4 DVO_A_[7:0] OCLK_P TVP5158 8-C h CIF 8Bit@54MH z VPIF_A DVO_D_[7:0] OCLKN/CLKIN I2 C VIN_1 VIN_2 VIN_3 TVP5158 VIN_4 VIN_1 VIN_2 H.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 VIN_1 VIN_2 VIN_3 VIN_4 www.ti.com DVO_A_[7:0] OCLK_P TVP5158 8-Ch CIF + 1 -Ch D 1 VPIF_A 8Bit@108MHz DVO _C_[7:0] DVO_D_[7:0] OCLKN/CLKIN I2C VIN_1 VIN_2 VIN_3 DVO_A_[7:0] OCLK_P 4-C h CIF 8 Bit@ 27 MHz DVO_B _[7:0] TVP5158 H.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 3-11.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 3-12 and Table 3-13 show the bit assignment and field definition of 4-Byte start code for Active Video Line. Table 3-12. Bit Assignment of 4-Byte Start Code for Active Video Line BYTE 7 6 5 SC[3] 1 BOP EOP SC[2] 0 BOL EOL SC[1] ~LD_ID[6] SC[0] 1 4 3 2 RSVD 1 VCS_ID VDET 0 CH_ID[1:0] RSVD LN_ID[8:7] LN_ID[6:0] F V H P3 P2 P1 P0 Table 3-13.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 3-13. Bit Field Definition of 4-Byte Start Code for Active Video Line (continued) BIT NAME 7 1 6 F FUNCTION Always set to 1. F-bit 0: First field of frame 1: Second field of frame V-bit 5 V 0: when not in vertical blanking 1: during vertical blanking H-bit. Always set to 0.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 • • • • • • • • 3.9.2 www.ti.com Programmable Gain Amplifier (PGA) – Gain range: -12 ~ 0 dB, Gain Step: 1.
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TVP5158, TVP5157, TVP5156 www.ti.com 3.9.3 SLES243G – JULY 2009 – REVISED APRIL 2013 Serial Audio Interface The timing for the TVP5158 serial audio interface is shown in Figure 3-18. The TVP5158 audio data output (SD_R) and frame sync pulse (LRCLK) are aligned with the falling edge of the bit clock (BCLK). The TVP5158 audio data is delayed one BCLK cycles from the falling edge of the frame sync pulse. In the DSP mode, the TVP5158 frame sync pulse is high for only one BCLK cycle.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 3.9.5 www.ti.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 3-15.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 3.10 I2C Host Interface The I2C standard consists of two signals, serial input/output data line (SDA) and input/output clock line (SCL), which carry information between the devices connected to the bus. The input pins I2CA0, I2CA1 and I2CA2 are used to select the slave address to which the device responds. Although the I2C system can be multi-mastered, the TVP5158 decoder functions as a slave device only.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 I2C subaddress FFh contains 4 bits with each bit corresponding to one of the decoder cores. If a decoder read enable bit is set, then I2C read transactions are sent to the corresponding decoder core. If more than one decoder is enabled for reads, then the lowest numbered decoder that is enabled responds to the read transaction.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Read Phase 1 Step 1 0 I2C Start (master) S Step 2 7 6 5 4 3 2 1 0 1 0 1 1 X X X 0 2 I C General address (master) Step 3 9 I2C Acknowledge (slave) A Step 4 I2C Read register address (master) Step 5 I C Acknowledge (slave) 3 2 1 0 Addr Addr Addr Addr 0 Step 6 is optional.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 3.10.3 VBUS Access The TVP5158 video decoder has additional internal registers accessible through an indirect access to an internal 24-bit address wide VBUS. Figure 3-20 shows the VBUS registers access. 00h I2C Registers Comb Filter RAM 2 IC Host Processor VBUS Registers 00 0000h VBUS [23:0] E0h E1h E8h EAh 40 3E50h 40 3EEFh VBUS Data VBUS Address A0 3FFFh FFh Figure 3-20.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 3.11 Clock Circuits An analog clock multiplier PLL is used to generate a system clock from an external 27-MHz crystal (fundamental resonant frequency) or external clock reference input. A crystal can be connected across terminals 99 (XTAL_IN) and 101 (XTAL_OUT), or a 1.8-V external clock input can be connected to terminal 99.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 3.12 Reset Mode Terminal 3 (RESETB) is active low signal to hold the decoder into reset. Table 3-18 shows the configuration of reset mode. Table 3-19 describes the status of the decoder signals during and immediately after reset. Figure 3-22 shows the reset timing. After power-up, the device is in an unknown state until properly reset.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 4 Internal Control Registers 4.1 Overview The decoder is initialized and controlled by a set of internal registers which set all device operating parameters. Communication between the external controller and the decoder is through I2C. Table 4-1 shows the summary of these registers. The reserved registers must not be written. Reserved bits in the defined registers must be written with 0s, unless otherwise noted.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-1.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-3.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-6. RAM Version MSB Subaddress Default 7 05h Read only 6 5 4 3 RAM version MSB [7:0] 2 1 0 2 1 0 2 1 0 2 1 0 RAM version MSB [7:0] This register identifies the MSB of the RAM code revision number. Table 4-7. RAM Version LSB Subaddress Default 7 06h Read only 6 5 4 3 RAM version LSB [7:0] RAM version LSB [7:0] This register identifies the LSB of the RAM code revision number.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-10. Video Standard Status Subaddress Default 7 Autoswitch 0Ch Read only 6 5 4 3 2 Reserved 1 Video standard [2:0] 0 This register contains information about the detected video standard that the device is currently operating. When in autoswitch mode, this register can be tested to determine which video standard as has been detected. See subaddress: 0Dh.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-12. CVBS Autoswitch Mask Subaddress Default 7 Reserved 0Eh 03h 6 PAL 60 5 Reserved 4 NTSC 4.43 3 (Nc) PAL 2 (M) PAL 1 PAL 0 (M, J) NTSC Autoswitch mode mask Limits the video formats between which autoswitch is possible. PAL 60 0 Autoswitch does not include PAL 60 (default) 1 Autoswitch includes PAL 60 NTSC 4.43 0 Autoswitch does not include NTSC 4.43 (default) 1 Autoswitch includes NTSC 4.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-15. Luminance Contrast Subaddress Default 7 11h 80h 6 5 4 3 2 1 0 Contrast [7:0] Contrast [7:0] This register works for the luminance. See subaddress 12h.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-18. Chrominance Hue Subaddress Default 7 14h 80h 6 5 4 3 2 1 0 2 Color killer threshold [4:0] 1 0 Hue [7:0] Saturation [7:0] This register works for the chrominance. 0000 0000 -180° 1000 0000 0° (default) 1111 1111 +180° Table 4-19.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-20. Luminance Processing Control 1 Subaddress Default 7 NTSC_Ped 18h 40h 6 5 4 3 2 Reserved 1 Luminance signal delay [2:0] 0 NTSC_Ped Specifies whether NTSC composite video inputs are compliant with NTSC-M or NTSC-J. 0 NTSC-M (714/286 ratio, w/ pedestal) - default 1 NTSC-J (714/286 ratio, w/o pedestal) Luminance signal delay [2:0] Luminance signal delays respect to chroma signal in 1x pixel clock increments.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-22.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-23. Chrominance Processing Control 1 Subaddress Default 7 1Bh 00h 6 5 Reserved 4 Color PLL reset 3 Chroma adaptive comb enable 2 Reserved 1 0 Automatic color gain control [1:0] Color PLL reset 0 Color subcarrier PLL not reset (default) 1 Color subcarrier PLL reset Chrominance adaptive comb enable This bit is effective on composite video only.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-25. AGC Gain Status Subaddress Default 20h-21h Read Only Subaddress 20h 21h 7 6 5 4 3 2 Fine Gain [7:0] Fine Gain [13:8] Reserved 1 0 These AGC gain status registers are updated automatically when the AGC is enabled; in manual gain control mode these register values are not updated.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-29. Luma ALC Freeze Upper Threshold Subaddress Default 7 26h 00h 6 5 4 3 Luma ALC freeze [7:0] 2 1 0 Upper hysteresis threshold for luma ALC freeze function. The lower hysteresis threshold for the ALC freeze function is fixed at 1 count out of 4096. Setting the upper threshold to 00h (default condition) disables the ALC freeze function. Table 4-30.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-33. AGC Decrement Speed Subaddress Default 7 2Bh 04h 6 5 Reserved 4 3 2 1 AGC decrement speed [2:0] 0 AGC decrement speed Controls the filter coefficient of the first-order recursive automatic gain control (AGC) algorithm when decrementing the gain. NOTE: This register affects the decrement speed only when the amplitude reference used by the AGC is either the composite peak or the luma peak.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-35. AGC White Peak Processing Subaddress Default 2Dh F2h 7 6 5 4 3 Luma peak A Reserved Color burst A Sync height A Luma peak B 2 Composite peak 1 0 Color burst B Sync height B If all four bits of the lower nibble are set to logic 1 (that is, no amplitude reference selected), then the front-end analog and digital gains are automatically set to nominal values.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-36. Back-End AGC Control Subaddress Default 2Eh 08h 7 6 5 4 3 1 Reserved 2 Peak 1 Color 0 Sync This register allows disabling the back-end AGC when the front-end AGC uses specific amplitude references (sync-height, color burst or composite peak) to decrement the front-end gain.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-38. AVID Start Pixel Subaddress Default Subaddress 48h 49h 48h-49h 007Ah/0084h 7 6 5 4 3 AVID start [7:0] AVID active Reserved 2 1 Reserved 0 AVID start [9:8] AVID start [9:0] AVID start pixel number, this is a absolute pixel location from HS start pixel 0. The TVP5158 updates the AVID start only when the AVID start MSB byte is written to. AVID start pixel register also controls the position of SAV code.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-41. Noise Reduction Control Subaddress Default 5Dh 09h 7 6 5 4 NR_Color_ Killer_En Reserved 3 Block_Width_ UV 2 1 0 Block_Width_Y Test_ Bypass NR_ Bypass NR_Color_Killer_En Noise reduction color killer enabled 0 Disabled (default) 1 Enabled Block_Width_UV Number of UV pixel values which the algorithm uses to generate the noise average.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-43. Operation Mode Control Subaddress Default 7 V-PLL free run 60h 00h 6 Reserved 5 4 H-PLL Response Time 3 V-bit control 2 Freeze C-PLL 1 0 Reserved V-PLL free run mode 0 Disabled (default) 1 Enabled H-PLL Response Time When in the Normal mode, the horizontal PLL (H-PLL) response time is set to its slowest setting.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-45. Sync Height Low Threshold Subaddress Default 7 7Ch 02h 6 5 4 3 VSync upper thres [7:0] 2 1 0 1 0 1 0 Clear lost lock detect Lower hysteresis threshold for vertical sync-height detection (value/32×target sync height). Table 4-46.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-49. 656 Version/F-bit Control Subaddress Default 7 87h 00h 6 5 4 3 2 Reserved 656 version 0 1 F-control 0 1 64 1 656 version 0 F-control Timing confirms to ITU-R BT.656-4 specifications (default) Timing confirms to ITU-R BT.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-50.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-51. F-Bit and V-Bit Control Subaddress Default 7 Rabbit 89h 16h 6 5 Reserved 4 Fast lock 3 2 F and V [1:0] 1 Phase Det 0 HPLL Rabbit Enable "rabbit ear" 0 Disabled (default) 1 Enabled Fast lock Enable fast lock where vertical PLL is reset and a 2 second timer is initialized when vertical lock is lost; during timeout the detected input VS is output.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-53. Auto Contrast User Table Index Subaddress Default 7 Reserved 8Fh 04h 6 5 AC_User_Mode_Table [2:0] 4 3 2 1 0 1 0 Reserved AC_User_Mode_Table [2:0] User table selection for auto contrast user mode when the register 0Fh sets to 02h. 000 Brighter 1 001 Brighter 2 010 Brighter 3 (Brightest) 011 Darker 1 100 Darker 2 101 Darker 3 (Darkest) 110 to Reserved 111 Table 4-54.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-56. Blue Screen Cr Control Subaddress Default 92h 80h 7 6 5 4 3 2 1 0 Cr value [9:2] The Cr value of the color screen output when enabled by bit 2 or 3 of the Output Formatter 2 register is programmable using a 10-bit value. The 8 MSBs, bits[9:2], are represented in this register. The remaining two LSB are found in the Blue Screen LSB register. The default color screen output is black.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-61. Noise Reduction Y/U/V T0 Subaddress Default 9Eh 0Ah 9Fh BCh A0h BCh Subaddress 9Eh 9Fh A0h 7 6 5 4 3 Noise Reduction Y T0 [7:0] Noise Reduction U T0 [7:0] Noise Reduction V T0 [7:0] 2 1 0 These registers control how much noise filtering is done for Y/U/V channels. The higher the value is, the more noise filtering at the expense of video details. Table 4-62.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-64. Output Formatter Control 2 Subaddress Default 7 A9h 40h 6 5 4 3 2 Blue screen output [1:0] Reserved 1 0 Reserved This register should be written to all four video decoder cores. Blue screen output [1:0] Fully programmable color of "blue screen" to support clean input/channel switching.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-67. Embedded Sync Offset Control 2 Subaddress Default 7 AFh 00h 6 5 4 3 2 1 0 Offset [7:0] Offset [7:0] This register allows the line relationship between the embedded F and V bit signals to be offset from the 656 standard positions, and moves F relative to V. This register is only applicable to input video signals with a standard number of lines per frame.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-68. AVD Output Control 1 Subaddress Default B0h 00h 7 6 Interleave_mode 5 4 Channel_Mux_Number 3 Output_ type 2 VCS_ID 1 0 Video_Res_Sel This register should be written to all four video decoder cores. Interleave_mode Interleave mode for multi-channel formats 00 Non-interleaved (a.k.a.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-69. AVD Output Control 2 Subaddress Default B1h 10h 7 6 LLC_En Line_Crop_En 5 4 Quan_Ctrl 3 Line_ID_Ctrl 2 Chan_ID_ SAVEAV_En 1 Chan_ID_ Blank_En 0 Video_Det_ SAVEAV_En This register should be written to all four video decoder cores. LLC_En Line-locked clock enable, active high. For non-interleaved mode only. For use with Port A only. For D1 resolution only.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-70. OFM Mode Control Subaddress Default 7 Video_Port_B_ En B2h 20h 6 Out_CLK_ Freq_Ctl 5 OSC_OUT_En 4 Out_CLK_ Pol_Sel 3 Out_CLK_ Freq_Sel 2 Out_CLK_P_En 1 Out_CLK_N_E n 0 Video_Port_En This register only needs to be written to video decoder core 0.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-71. OFM Channel Select 1 Subaddress Default B3h E4h 7 6 Chan_Sel_Port_D 5 4 Chan_Sel_Port_C 3 2 Chan_Sel_Port_B 1 0 Chan_Sel_Port_A This register only needs to be written to video decoder core 0. OFM channel select by video port in 1-Ch mode.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-72. OFM Channel Select 2 Subaddress Default B4h E4h 7 6 2nd_Chan_Sel_Port_B 5 4 1st_Chan_Sel_Port_B 3 2 2nd_Chan_Sel_Port_A 1 0 1st_Chan_Sel_Port_A This register only needs to be written to video decoder core 0. OFM channel select by video port in 2-Ch mode.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-74. OFM Super-Frame Size Subaddress Default B6h-B7h 041Bh Subaddress B6h B7h 7 6 5 4 3 Super_Frame_Size [7:0] Ctrl_Mode [1:0] Reserved 2 1 0 Super_Frame_Size [11:8] These registers write to decoder core 0 only.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-76. Misc OFM Control Subaddress Default 7 BAh 00h 6 5 4 3 2 1 Reserved 0 OFM_Soft_ Reset OFM_Soft_Reset Soft reset for OFM logic. NOTE: This bit is automatically cleared by firmware when the reset is completed. 0 Normal operation (default) 1 Reset output formatter logic NOTE: In cascade mode, the OFM reset of the 1st stage should be asserted after the OCLK_N output of the 2nd stage is enabled. Table 4-77.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-78. Analog Audio Gain Control 1 Subaddress Default 7 C1h 88h 6 5 Audio_Gain_Ctrl_CH2 4 3 2 1 Audio_Gain_Ctrl_CH1 0 Audio_Gain_Ctrl_CH2 Analog audio gain control for audio Ch 2. See values below. Audio_Gain_Ctrl_CH1 Analog audio gain control for audio Ch 1 0000 -12.0 dB 0001 -10.5 dB 0010 -9 dB 0011 -7.5 dB 0100 -6 dB 0101 -4.5 dB 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 -3 dB -1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-79. Analog Audio Gain Control 2 Subaddress Default 7 C2h 88h 6 5 Audio_Gain_Ctrl_CH4 4 3 2 1 Audio_Gain_Ctrl_CH3 0 Audio_Gain_Ctrl_CH4 Analog audio gain control for audio Ch 4. See values below. Audio_Gain_Ctrl_CH3 Analog audio gain control for audio Ch 3 0000 -12.0 dB 0001 -10.5 dB 0010 -9 dB 0011 -7.5 dB 0100 -6 dB 0101 -4.5 dB 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 80 -3 dB -1.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-80. Audio Mode Control Subaddress Default C3h C9h 7 6 5 SD_M_En SD_R_En I2S_Mode 4 Serial_IF_Form at 3 BCLK_R_Freq 2 1 Audio_Data_Format 0 TDM_Pin_Sel SD_M_En SD_M output enable, active high 0 SD_M output disabled 1 SD_M output enabled (default) SD_R_En SD_R output enable, active high.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-81.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-82. Audio Mute Control Subaddress Default 7 C5h 00h 6 5 4 Reserved 3 Ch4_Mute 2 Ch3_Mute 1 Ch2_Mute 0 Ch1_Mute Ch4_Mute Ch 4 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17). 0 Disabled (default) 1 Enabled Ch3_Mute Ch 3 Audio mute enable, active high. Affects the audio mixer output (SD_M) only (see Figure 3-17).
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-84. Analog Mixing Ratio Control 2 Subaddress Default C7h 00h 7 6 5 Audio_Mixing_Ratio_CH4 4 3 2 1 Audio_Mixing_Ratio_CH3 0 Audio_Mixing_Ratio_CH4 Audio mixing ratio for audio channel 4. See values below. Audio_Mixing_Ratio_CH3 Audio mixing ratio for audio channel 3 0000 0.25 (default) 0001 0.31 0010 0.38 0011 0.44 0100 0.5 0101 0.63 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 0.75 0.88 1.00 1.25 1.5 1.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-87. Super-Frame SAV2EAV Duration Status Subaddress Default D2h-D3h Read Only Subaddress D2h D3h 7 6 5 4 3 SAV2EAV [7:0] 2 Reserved 1 0 EAV2SAV [10:8] SAV2EAV [10:0] Super-frame SAV2EAV duration (bytes). For line-interleaved mode only. Table 4-88.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-91. Interrupt Status Subaddress Default F2h Read Only 7 6 Reserved 5 Sig_Present 4 Weak_Sig 3 V_Lock 2 Macrovision 1 Vid_Std 0 Reserved The host interrupt status register represents the interrupt status after applying mask bits. Therefore, the status bits are the result of a logical AND between the raw status and mask bits.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-92. Interrupt Mask Subaddress Default 7 F4h 00h 6 Reserved 5 Sig_Present 4 Weak_Sig 3 V_Lock 2 Macrovision 1 Vid_Std 0 Reserved The host interrupt mask register can be used by the external processor to mask unnecessary interrupt sources for the interrupt status register bits, and for the external interrupt pin. The external interrupt is generated from all non-masked interrupt flags.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com Table 4-93. Interrupt Clear Subaddress Default 7 F6h 00h 6 5 Sig_Present Reserved 4 Weak_Sig 3 V_Lock 2 Macrovision 1 Vid_Std 0 Reserved The host interrupt clear register is used by the external processor to clear the interrupt status bits in the host interrupt status register. When no non-masked interrupts remain set in the register, the external interrupt pin also becomes inactive.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Table 4-95. Decoder Read Enable Subaddress Default 7 FFh 01h 6 5 Reserved Addr Auto Incr 4 Decoder Auto Incr 3 2 1 0 Decoder 4 Decoder 3 Decoder 2 Decoder 1 This register controls which of the four decoder cores responds to I2C read transactions. A 1 in the corresponding bit position enables the decoder to respond to read commands. A 1 in Decoder Auto Increment reads the next byte from the next enabled decoder.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 5 Electrical Specifications 5.1 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) VDD Supply voltage range VDD_3_3 to VSS_3_3 0.5 V to 4.0 V VDD_1_1 to VSS_1_1 -0.2 V to 1.2 V VDDA_3_3 to VSSA_3_3 -0.3 V to 3.6 V VDDA_1_8 to VSSA_1_8 -0.2 V to 2.0 V VDDA_1_1 to VSSA_1_1 -0.2 V to 1.2 V VI Digital input voltage range VI to DGND -0.5 V to 4.
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TVP5158, TVP5157, TVP5156 www.ti.com 5.2 SLES243G – JULY 2009 – REVISED APRIL 2013 Recommended Operating Conditions MIN NOM MAX VDD_3_3 Supply voltage, digital 3 3.3 3.6 V VDD_1_1 Supply voltage, digital 1 1.1 1.2 V VDDA_3_3 Supply voltage, analog 3 3.3 3.6 V VDDA_1_8 Supply voltage, analog 1.65 1.8 1.95 V VDDA_1_1 Supply voltage, analog 1 1.1 1.2 V VI(pp) Analog video input voltage (ac-coupling necessary) (1) 1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 5.4 Electrical Characteristics 5.5 DC Electrical Characteristics For minimum/maximum values: VDD_1_1 = 1.0 to 1.2 V, VDD_3_3 = 3.0 V to 3.6 V, VDDA_1_1 = 1.0 V to 1.2 V, VDDA_1_8 = 1.65 V to 1.95 V, VDDA_3_3 = 3.0 V to 3.6 V For typical values (TA = 25°C): VDD_1_1 = 1.1 V, VDD_3_3 = 3.3 V, VDDA_1_1 = 1.1 V, VDDA_1_8 = 1.8 V, VDDA_3_3 = 3.3 V (1) PARAMETER TEST CONDITIONS IDD(33D) 3.
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TVP5158, TVP5157, TVP5156 www.ti.com 5.6 SLES243G – JULY 2009 – REVISED APRIL 2013 Video A/D Converters Electrical Characteristics ADC sample rate = 27 MSPS for video Ch 1, Ch 2, Ch 3, Ch 4 PARAMETER TEST CONDITIONS MIN Video ADC conversion rate TYP MAX 27 Zi Input impedance, analog video inputs (1) Ci Input capacitance, analog video inputs (1) Vi(PP) Full-scale input range of ADC (2) MHz 200 kΩ 10 Ccoupling = 0.1 µF 1.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 5.8 www.ti.com Video Output Clock and Data Timing 10-pF load for 27 MHz and 54 MHz, 6-pF load for 108 MHz NO. PARAMETER Duty cycle, OCLK_P/OCLK_N t3 t4 Fall time, OCLK_P/OCLK_N Rise time, OCLK_P/OCLK_N t1 Fall time, Data t2 Rise time, Data t5 Propagation delay from falling edge of OCLK_P/OCLK_N TEST CONDITIONS MIN TYP ≤50%, OCLK_P/OCLK_N = 108 MHz 44 50 MAX UNIT 55 % 90% to 10%, OCLK_P/OCLK_N = 27 MHz 1.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 I2C Host Port Timing (1) 5.9 NO. PARAMETER MIN TYP MAX UNIT t1 Bus free time between STOP and START 1.3 µs t2 Data Hold time t3 Data Setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 ns t6 Hold time (repeated) START condition 0.6 t7 Rise time SDA and SCL signal 250 0 0.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com I2S Port Timing 5.9.1 NOTE Philips I2S bus compliant (specified by design) – See the Philips I2S bus specification 5.10 Miscellaneous Timings PARAMETER tRESET RESETB Signal Low Time for valid reset tvalid I2C valid time, Initialization time after reset until I2C ready MIN TYP MAX UNIT 20 ms 260 µs 5.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 6 Application Information 6.1 4-Ch D1 Applications 4-Ch D1 8Bit@108MHz Figure 6-1. 4-Ch D1 Application (Single BT.656 Interface) DVO_A_[7:0] DVO_B_[7:0] OCLK_P VIN_1 VIN_2 TVP5158 VIN_3 Multi-Ch Video Decoder 4-Ch D1 16Bit@54MHz I2C VPIF-A VPIF-B H.264/MPEG-4 4-Ch D1 Recording DM6467 DaVinci HD Multi-Ch D1 Preview VIN_4 Figure 6-2. 4-Ch D1 Application (16-Bit YCbCr 4:2:2 Interface) 6.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com 4-Ch Half-D1 + 1-Ch D1 8Bit@108MHz 4-Ch Half-D1 + 1-Ch D1 8Bit@108MHz NOTE: The backend DSP drops one field of Half-D1 to get CIF format video Figure 6-4. 8-Ch CIF Real Time Encoding and Multi-Ch D1 Preview Application 6.3 16-Ch CIF Applications See Section 3.8.3.3 for the details of 16-Ch CIF applications.
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TVP5158, TVP5157, TVP5156 www.ti.com 6.4 SLES243G – JULY 2009 – REVISED APRIL 2013 Application Circuit Examples U1A C70 108 R54 R50 J1B 0.1 µF 109 37.4 W VIN_1_P VIN_1_N DVO_A_0 DVO_A_1 DVO_A_2 DVO_A_3 DVO_A_4 DVO_A_5 DVO_A_6 DVO_A_7 78 77 75 74 72 71 69 68 C71 9 75 W 112 3 R55 10 0.1 µF 113 R51 37.4 W 75 W 121 R56 0.1 µF 122 R52 12 75 W VIN_3_P VIN_3_N DVO_B_0 DVO_B_1 DVO_B_2 DVO_B_3 DVO_B_4 DVO_B_5 DVO_B_6 DVO_B_7 63 62 60 59 57 56 54 53 37.4 W C73 RCA_Octal_stack 125 R57 0.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com U1B C65 J1A 95 5 1 2.2 µF R60 5.6 kW 6 7 2.2 µF AIN_2 SD_R 89 88 C67 R62 93 2.2 µF 5.6 kW 8 SD_M 94 R61 5.6 kW 2 AIN_1 C66 AIN_3 LRCLK_R C68 R63 92 5.6 kW 2.2 µF BCLK_R 86 85 AIN_4 RCA_Octal_stack 16 R64 R65 R66 R67 5.6 kW 5.6 kW 5.6 kW 5.6 kW 17 19 SD_CO 83 LRCLK_CI BCLK_CI SD_CI TVP5158 NOTE: System level ESD protection is not included in above application circuit but is recommended.
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TVP5158, TVP5157, TVP5156 www.ti.com SLES243G – JULY 2009 – REVISED APRIL 2013 Revision History NOTE: Page numbers for previous revisions may differ from page numbers in the current version. REVISION SLES243 SLES243A COMMENTS Initial release Table 2-1, XTAL_REF description change. Figure 3-21, 0-Ω resistor added inline between XTAL_REF pin and VSSA. SLES243B YUV references changed to YCbCr. Section 1, Trademarks added.
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TVP5158, TVP5157, TVP5156 SLES243G – JULY 2009 – REVISED APRIL 2013 www.ti.com REVISION SLES243E COMMENTS Table 4-1, Added RAM version MSB and LSB registers (subaddress: 05h-06h). Table 4-6, Added RAM version MSB register (subaddress: 05h). Table 4-7, Added RAM version LSB register (subaddress: 06h). Section 5.1, Updated VESD limits. SLES243F Table 3-11, Super-frame format and timing information modified.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Aug-2013 (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TVP5157PNPR HTQFP PNP 128 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q1 TVP5158IPNPR HTQFP PNP 128 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.0 Q1 TVP5158PNPR HTQFP PNP 128 1000 330.0 24.4 17.0 17.0 1.5 20.0 24.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Mar-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TVP5157PNPR HTQFP PNP 128 1000 367.0 367.0 55.0 TVP5158IPNPR HTQFP PNP 128 1000 367.0 367.0 55.0 TVP5158PNPR HTQFP PNP 128 1000 367.0 367.0 55.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.