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TVP5160

NTSC/PAL/SECAM/Component 2x10-Bit Digital Video

Decoder

Data Manual

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Literature Number: SLES135E

February 2005–Revised April 2011

Summary of content (111 pages)

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TVP5160 NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder Data Manual PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Contents 1 2 2 ........................................................................................................................ 9 1.1 Features ...................................................................................................................... 9 1.2 Applications .................................................................................................................. 9 1.3 Description ....................
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TVP5160 www.ti.com 3 4 5 6 7 8 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 ................................................................................................... 38 3.1 Register Definitions ........................................................................................................ 43 3.2 VBUS Register Definitions ............................................................................................... 88 Typical Application Circuit .....................................
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com List of Figures .................................................................................. ...................................................................................... Luminance Edge-Enhancer Peaking Block ................................................................................... Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling...............................................
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com List of Tables .............................................................................................................. 1-1 Terminal Functions 2-1 Y/C Separation Support by Video Standard .................................................................................. 20 2-2 Output Format ....................................................................................................................
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 3-36 3-37 3-38 3-39 3-40 3-41 3-42 3-43 3-44 3-45 3-46 3-47 3-48 3-49 3-50 3-51 3-52 3-53 3-54 3-55 3-56 3-57 3-58 3-59 3-60 3-61 3-62 3-63 3-64 3-65 3-66 3-67 3-68 3-69 3-70 3-71 3-72 3-73 3-74 3-75 3-76 3-77 3-78 3-79 3-80 3-81 3-82 3-83 6 www.ti.com .................................................................................................................... .....................................................................................
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TVP5160 www.ti.com SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 .......................................................................................................... .......................................................................................................... AGC Increment Delay ........................................................................................................... Analog Output Control 1 ...............................................................................
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 3-132 3-133 3-134 3-135 3-136 3-137 3-138 3-139 3-140 3-141 3-142 3-143 3-144 3-145 3-146 3-147 3-148 3-149 3-150 6-1 8-1 8 www.ti.com ................................................................................................................. ................................................................................................................. Interrupt Clear 0 .........................................................................
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com NTSC/PAL/SECAM/Component 2x10-Bit Digital Video Decoder Check for Samples: TVP5160 1 Introduction 1.1 Features 1 • Two 11-Bit 60-MSPS Analog-to-Digital (A/D) Converters With Analog Preprocessors (Clamp/AGC) • Fixed RGB-to-YUV Color Space Conversion • Robust Sync Detection for Weak and Noisy Signals as Well as VCR • Supports NTSC (J, M, 4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com alternately, then decimated to the 1× rate. Composite or S-Video signals are sampled at 4× the ITU-R BT.601 clock frequency (54 MHz), line-locked for correct pixel alignment, and are then decimated to the 1× rate. CVBS decoding uses advanced 3D Y/C filtering and 2-dimensional complementary 5-line adaptive comb filtering for both the luma and chroma data paths to reduce both cross-luma and cross-chroma artifacts.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com • • • • • • • • • • • generate an output video stream. This improves the overlay picture quality when the external FSO and digital RGB signals are generated by an asynchronous source. SCART 4x oversampled fast switching between component RGB input and CBVS input The SCART overlay control signal (FSS) is oversampled at 4x the pixel clock frequency. The phase of this signal is used to mix between the CVBS input and the analog RGB inputs.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 • • 1.4 TVP5146M2 TVP5147M1 TVP5150AM1 TVP5151 TVP5154A TVP5158 Trademarks • • • • 1.6 progressive signals Reduced power consumption: 1.8-V digital core, 3.3-V and 1.8-V analog core with power-save and power-down modes 128-TQFP PowerPAD™ package Related Products • • • • • • 1.5 www.ti.com TI and PowerPAD are trademarks of Texas Instruments. Macrovision is a trademark of Macrovision Corporation.
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VI_10 VI_9 VI_8 Sampling Clock ADC2 ADC1 Analog Front End M U X 3D/5-line Adaptive Comb Filter C Y/C Separation Y Timing Processor With Sync Detector C/CbCr CVBS/Y VBI Data Slicer Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.com: TVP5160 TBC/ IF Comp C Chroma C Processing Luma Y Processing Host Interface C Y INTREQ SDRAM Interface 3D Noise Reduction Y Output Formatter GPIO FSO DR DG DB Y[9:0] C[9:0] www.ti.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 1.9 www.ti.com Terminal Assignments The TVP5160 video decoder is packaged in a 128-terminal PNP PowerPAD package. Figure 1-1 is the PNP-package terminal diagram. Table 1-1 gives a description of the terminals.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 1-1. Terminal Functions PIN NAME NO. I/O DESCRIPTION Analog Video VI_1 VI_2 VI_3 VI_4 VI_5 VI_6 VI_7 VI_8 VI_9 VI_10 VI_11 VI_12 3 4 5 7 8 9 17 18 19 21 22 23 I VI_x: analog video inputs Up to 12 composite, 6 S-Video, or 3 component video inputs (or combinations thereof) can be supported. Also, 4-channel SCART is supported. The inputs must be ac-coupled. The recommended coupling capacitor is 0.1 µF.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 1-1. Terminal Functions (continued) PIN NAME NO. I/O DESCRIPTION Power Supplies A33GND 1, 26, 27, 28, 126, 128 P Analog 3.3-V return. Connect to analog ground. A33VDD 2, 25, 125 P Analog power. Connect to analog 3.3-V supply. A18GND 12, 14, 15 P Analog 1.8-V return. Connect to analog ground. A18VDD 11, 13, 16 P Analog power. Connect to analog 1.8-V supply. PLL18GND 124 P Analog power return.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 2 Functional Description 2.1 Analog Processing and A/D Converters Figure 2-1 shows a functional diagram of the analog processors and A/D converters (ADCs). This block provides the analog interface to all video inputs. It accepts up to 12 inputs and performs source selection, video clamping, video amplification, A/D conversion, and gain and offset adjustments to center the digitized video signal.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 2.1.1 www.ti.com Video Input Switch Control The TVP5160 decoder has two analog channels that accept up to 12 video inputs. The user can configure the internal analog video switches via I2C.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 2.1.6 A/D Converters All ADCs have a resolution of 11 bits and can operate up to 60 MSPS. All A/D channels receive an identical clock from the on-chip, phase-locked loop (PLL) at a frequency between 24 MHz and 60 MHz. All ADC reference voltages are generated internally. 2.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 2.2.4 www.ti.com Y/C Separation Y/C separation may be done using 3D or 2D adaptive 5-line (5-H delay) comb filters or chroma trap filter for both NTSC and PAL video standards as shown in Table 2-1. The comb filter can be selectively bypassed in the luma or chroma path. If the comb filter is bypassed in the luma path, then chroma notch filters are used.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 2.2.8 Luminance Processing The luma component is derived from the composite signal by subtracting the remodulated chroma information. The luminance signal is then fed to the input of a peaking circuit. Figure 2-2 illustrates the basic functions of the luminance data path. In the case of S-Video, the luminance signal bypasses the comb filter or chroma trap filter and is fed to the circuit directly.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 2.3 www.ti.com Clock Circuits An internal line-locked PLL generates the system and pixel clocks. A 14.31818-MHz clock is required to drive the PLL. This may be input to the TVP5160 decoder at 1.8-V level on terminal 121 (XIN), or a crystal of 14.31818-MHz fundamental resonant frequency may be connected across terminals 121 (XIN) and 122 (XOUT).
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Valid Sample Valid Sample Reserved RTC Mode 18 CLK 128 CLK M S B L S B 22 0 45 CLK 23-Bit Fsc PLL Increment S R 3 CLK 1 CLK Start Bit Figure 2-5. RTC Timing RTC: Reset bit (R) is active low Sequence bit (S) PAL: 1 = (R-Y) line normal 0 = (R-Y) line inverted NTSC: 1 = no change 2.5 Output Formatter The output formatter sets how the data is formatted for output on the TVP5160 output buses.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 2-3. Summary of Line Frequency, Data Rate, and Pixel/Line Counts PIXELS PER LINE ACTIVE PIXELS PER LINE LINES PER FRAME PIXEL FREQ (MHz) COLOR SUBCARRIER FREQUENCY (MHz) HORIZONTAL LINE RATE (kHz) NTSC-J, M 858 720 525 13.5 3.579545 15.73426 NTSC-4.43 858 720 525 13.5 4.43361875 15.73426 PAL-M 858 720 525 13.5 3.57561149 15.73426 PAL-60 858 720 525 13.5 4.43361875 15.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com R R’ G G’ B B’ 4× Oversample FSS FSO D FSS’ FSO’ D D R” R’’’ G” G’’’ B” B’’’ Y Color Space Conversion U V Gain/Offset Y’ Gain UV’ UV 2 Y’’ FSS” FSO” Prog Delay FSS’’’ D FSO’’’ SCART/COMP_Y SCART/COMP_UV Output Formatter Soft Mix UV’’ SCART/COMP_Y’ SCART/COMP_UV’ CVBS_SEP_Y CVBS_SEP_UV D = User Prgrammable Delay Figure 2-6. Fast-Switches for SCART and Digital Overlay Table 2-4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 2-5. Look-Up Table for Converting from Digital RGB to 10-Bit YCbCr Data COLOR 2.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 525-Line 525 1 2 3 4 5 6 7 8 9 10 20 11 21 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 262 263 VBLK Stop 264 265 266 267 268 269 270 271 272 273 283 284 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-7.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 625-Line 622 623 624 625 1 2 3 4 5 6 7 8 23 24 25 First Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start 310 311 VBLK Stop 312 313 314 315 316 317 318 319 320 321 336 337 338 Second Field Video HS VS VS Start VS Stop CS FID VBLK VBLK Start A. VBLK Stop NOTE: Line numbering conforms to ITU-R BT.470. Figure 2-8. Vertical Synchronization Signals for 625-Line System ITU-R BT.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 0 SCLK Y[9:0] Cb Y Cr Y EAV 1 EAV 2 EAV 3 EAV 4 Horizontal Blanking HS Start SAV 1 SAV 2 SAV 3 SAV 4 Cb0 Y0 Cr0 Y1 HS Stop HS A C B D AVID AVID Stop AVID Start Figure 2-9. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode SCLK = 2× PIXEL CLOCK (1) A B C D NTSC 601 MODE 106 128 42 276 PAL 601 112 128 48 288 480p 106 128 42 276 576p 112 128 48 288 (1) ITU-R BT.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 0 SCLK Y[9:0] Y Y Y Y Horizontal Blanking Y0 Y1 Y2 Y3 CbCr[9:0] Cb Cr Cb Cr Horizontal Blanking Cb0 Cr0 Cb1 Cr1 HS Start HS Stop HS A C B D AVID AVID Stop AVID Start NOTE: AVID rising edge occurs 4 clock cycles early. NOTE: AVID rising edge occurs 4 clock cycles early. Figure 2-10.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com HS First Field B/2 B/2 VS HS H/2 + B/2 Second Field H/2 + B/2 VS Figure 2-11. VS Position With Respect to HS for Interlaced Signals HS B/2 B/2 VS Figure 2-12. VS Position With Respect to HS for Progressive Signals 10-BIT (SCLK = 2× PIXEL CLOCK) MODE (1) H/2 B/2 H/2 NTSC 601 interlaced 64 858 32 429 PAL 601 interlaced 64 864 32 432 NTSC 601 progressive 858 32 PAL 601 progressive 864 32 (1) 2.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 2-6. EAV and SAV Sequence Y9 (MSB) Y8 Y7 Y6 Y5 Y4 Y3 Y2 Y1 Y0 Preamble 1 1 1 1 1 1 1 1 1 1 Preamble 0 0 0 0 0 0 0 0 0 0 Preamble 0 0 0 0 0 0 0 0 0 0 Status 1 F V H P3 P2 P1 P0 0 0 I2C Host Interface 2.9 Communication with the TVP5160 decoder is via an I2C host interface.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com I2C Operation 2.9.2 Data transfers occur utilizing the following formats.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 2.9.3.1 www.ti.com VBUS Write Single byte S B8 ACK S E8 B8 ACK ACK VA0 ACK E0 VA1 ACK ACK VA2 send data ACK ACK P P Multiple bytes S B8 S ACK B8 2.9.3.2 E8 ACK E1 ACK ACK VA0 ACK send data VA1 ACK ACK ...
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 2-9. Supported VBI System (continued) VBI SYSTEM STANDARD Gemstar EPG 1× NTSC LINE NUMBER NUMBER OF BYTES Gemstar EPG 2× NTSC User Any Programmable Programmable CGMS-A packet A 480p 41 20 bits CGMS-A packet B 480p 40 16 bytes 2 5 with frame byte 2.10.1 VBI FIFO and Ancillary Data in Video Stream Sliced VBI data can be output as ancillary data in the video stream in ITU-R BT.656 mode.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 0/1 – Transaction video line number [9:8] 2 – Match 2 flag 3 – Match 1 flag 4 – 1b if at least one error was detected in the EDC block. 0b if no error was detected. IDID1: Bit Bit Bit Bit CS: Sum of Y7–Y0 of byte 8 through byte 4N+5. For teletext modes, byte 8 is the sync pattern byte. Byte 9 is Sample 1. Fill byte: Fill byte makes a multiple of 4 bytes from byte zero to last fill byte 2.10.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 1 µs 200 µs Power Crystal RESET I 2C SDA Figure 2-14. Reset Timing After reset has completed, the following sequence of operations must be completed: 1. Write 01h to VBus register 0xB00060 2. Write 01h to VBus register 0xB00063 3. Write 00h to VBus register 0xB00060 2.12 Adjusting External Syncs The TVP5160 decoder stores values for the positions of the external syncs for two different modes: • 525-line with ITU-R BT.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 3 www.ti.com Internal Control Registers The TVP5160 decoder is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP5160 decoder is through a standard I2C host port interface, as described earlier. Table 3-1 shows the summary of these registers.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-1.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-1.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-1.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-2.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 3.1 Register Definitions Table 3-3. Input/Output Select Subaddress Default 00h 00h 7 6 5 4 3 Input select [7:0] 2 1 0 Twelve input terminals can be configured to support composite, S-Video, and component YPbPr. Only values in Table 3-4 are valid. NOTE: The video output can be either CVBS, Y, or G. Table 3-4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-5. AFE Gain Control Subaddress Default 01h 0Fh 7 6 5 4 Reserved Bit 3: Bit 2: Bit 1: AGC: 3 1 2 1 1 1 0 AGC 1b must be written to this bit 1b must be written to this bit 1b must be written to this bit Controls automatic gain 0 = Manual 1 = Enable auto gain (default) This setting only affects the analog front-end (AFE). The brightness and contrast controls are not affected by these settings. Table 3-6.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-8. Autoswitch Mask Subaddress Default 04h 23h 7 Reserved 6 PAL 60 5 SECAM 4 NTSC 4.43 3 (Nc) PAL 2 (M) PAL 1 PAL 0 (M, J) NTSC Autoswitch mode mask: Limits the video formats between which autoswitch is possible. See register 30h for masking the progressive modes.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-10. Luminance Processing Control 1 Subaddress Default 06h 00h 7 Reserved 6 Pedestal 5 Reserved 4 VBI raw 3 Reserved 2 1 Luminance signal delay [2:0] 0 Pedestal: 0 = 7.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-12. Luminance Processing Control 3 Subaddress Default 08h 00h 7 6 5 4 3 2 Reserved 1 0 Trap filter select [1:0] Trap filter select[1:0] selects one of the four trap filters to produce the luminance signal by removing the chrominance signal from the composite video signal. The stop band of the chroma trap filter is centered at the chroma subcarrier frequency with stopband bandwidth controlled by the two control bits.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-15. Chrominance Saturation Subaddress Default 0Bh 80h 7 6 5 4 3 2 1 0 Saturation [7:0] Saturation [7:0]: This register works for CVBS and S-Video chrominance. 0000 0000 = 0 (no color) 1000 0000 = 128 (default) 1111 1111 = 255 (maximum) For composite and S-Video outputs, the total chrominance gain relative to the nominal chrominance gain as a function of the Saturation [7:0] setting is as follows.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-17. Chrominance Processing Control 1 Subaddress Default 7 3DYC 0Dh 00h 6 5 TBC 4 Reserved 3 Chroma adaptive comb enable 2 3DNR 1 0 Automatic color gain control [1:0] 3DYC, frame recursive noise reduction (3DNR), and time base correction (TBC) can be used simultaneously or independently.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-18. Chrominance Processing Control 2 Subaddress Default 0Eh 0Ch 7 6 5 4 Reserved 3 PAL compensation 2 WCF 1 0 Chrominance filter select [1:0] This register trades chroma bandwidth for less false color. PAL compensation: This bit has no effect in NTSC and SECAM modes.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-21. B/Pb Saturation Subaddress Default 12h 80h 7 6 5 4 3 B/Pb saturation[7:0] 2 1 0 B/Pb saturation [7:0]: This register works only with YPbPr component video. For RGB video, use the AFE gain registers. 0000 0000 = minimum 1000 0000 = default 1111 1111 = maximum For component video, the total Pb gain relative to the nominal Pb gain as a function of the B/Pb saturation[7:0] setting is as follows.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-24. AVID Stop Pixel Subaddress Default Subaddress 18h 19h 18h–19h 325h/32Fh 7 6 5 4 3 AVID stop [7:0] 2 Reserved 1 0 AVID stop [9:8] AVID stop [9:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is a absolute pixel location from HS start pixel 0. The TVP5160 decoder updates the AVID stop only when the AVID stop MSB byte is written to.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-28. VS Stop Line Subaddress Default 20h–21h 004h/001h Subaddress 20h 21h 7 6 5 4 3 2 1 0 VS stop [7:0] Reserved VS stop [9:8] VS stop [9:0]: This is an absolute line number. The TVP5160 decoder updates the VS stop only when the VS stop MSB byte is written to. If these registers are modified, then the TVP5160 decoder retains the values for each video standard until the device is reset.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-32. Embedded Sync Offset Control 2 Subaddress Default 27h 00h 7 6 5 4 3 2 1 0 Offset [7:0] This register allows the line relationship between the embedded F bit and V bit signals to be offset from the 656 standard positions, and moves F relative to V. This register is only applicable to input video signals with standard number of lines.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-34. Fast-Switch Overlay Delay Subaddress Default 29h 17h 7 6 Reserved 5 4 3 2 FSO delay [4:0] 1 0 Overlay delay [4:0]: Adjusts delay between digital RGB and FSO 11111 = 8 pixel delay ⋮ 11000 = 1 pixel delay 10111 = 0 delay (default) 10110 = –1 pixel delay ⋮ 00000 = –23 pixel delay When SCART mode is active (RGB component) the recommended setting for this register is 1Bh; otherwise, 17h is recommended. Table 3-35.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-37. SCART Delay Subaddress Default 2Ch 56h 7 Reserved 6 5 4 3 SCART delay [6:0] 2 1 0 This register must be changed in multiples of 2 to maintain the CbCr relationship. SCART delay[6:0]: Adjusts delay between CVBS and component video. 101 1111 = 9 pixel delay ⋮ 101 0111 = 1 pixel delay 101 0110 = 0 delay (default) 101 0101 = –1 pixel delay ⋮ 000 0000 = –86 pixel delay Table 3-38.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-40. Component Autoswitch Mask Subaddress Default 30h 00h 7 6 5 4 Reserved 3 576i 2 480i 1 576p 0 480p 1 VS/VBLK 0 HS/CS Masks the component progressive/interlaced modes from being processed in the autoswitch routines.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-42. Output Formatter Control 1 Subaddress Default 7 Reserved 33h 40h 6 YCbCr code range 5 CbCr code 4 3 2 Reserved 1 Output format [2:0] 0 YCbCr output code range: 0 = ITU-R BT.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-44. Output Formatter Control 3 Subaddress Default 35h FFh 7 6 5 GPIO [1:0] 4 3 AVID [1:0] 2 1 GLCO [1:0] 0 FID [1:0] GPIO [1:0]: GPIO pin (pin 82) function select 00 = GPIO is 0b output 01 = GPIO is 1b output 10 = Reserved 11 = GPIO in logic input (default) AVID [1:0]: AVID pin function select 00 = AVID is 0b output 01 = AVID is 1b output 10 = AVID is active video indicator output 11 = AVID is logic input (default).
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-46. Output Formatter Control 5 Subaddress Default 37h FFh 7 6 5 C_5 [1:0] 4 3 C_4 [1:0] C_5 [1:0]: C_5 pin function select 00 = C_5 is 0b output 01 = C_5 is 1b output 10 = Reserved 11 = C_5 is logic input (default). C_4 [1:0]: C_4 pin function select 00 = C_4 is 0b output 01 = C_4 is 1b output 10 = Reserved 11 = C_4 is logic input (default).
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-48. Clear Lost Lock Detect Subaddress Default 7 39h 00h 6 5 4 Reserved 3 2 1 0 Clear lost lock detect Clear lost lock detect: Clear bit 4 (lost lock detect) in the status 1 register at subaddress 3Ah 0 = No effect (default) 1 = Clears bit 4 in the status 1 register Table 3-49.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-50.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-52. Video Standard Status Subaddress 7 Autoswitch 3Fh Read only 6 5 Reserved 4 3 2 1 Video standard [3:0] 0 Autoswitch mode 0 = Single standard set 1 = Autoswitch mode enabled Video standard [3:0]: CVBS and S-Video 0000 = Reserved 0001 = (M, J) NTSC 0010 = (B, D, G, H, I, N) PAL 0011 = (M) PAL 0100 = (Combination-N) PAL 0101 = NTSC 4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-54.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-57. AFE Coarse Gain for CH 2 Subaddress Default 47h 20h 7 6 5 4 3 2 CGAIN 2 [3:0] 1 0 1 0 1 0 Reserved CGAIN 2 [3:0]: Coarse Gain = 0.5 + (CGAIN 2)/10 where 0 ≤ CGAIN 2 ≤ 15. This register only works in manual gain control mode. When AGC is active, writing to any value is ignored. 1111 = 2 1110 = 1.9 1101 = 1.8 ⋮ 0010 = 0.7(default) 0001 = 0.6 0000 = 0.5 Table 3-58.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-60. AFE Fine Gain for B/Pb Subaddress Default Subaddress 4Ah 4Bh 4Ah–4Bh 900h 7 6 5 4 3 2 1 0 FGAIN 1 [7:0] Reserved FGAIN 1 [11:8] FGAIN 1 [11:0]: This fine gain applies to component B/Pb. Fine Gain = (1/2048) * FGAIN where 0 ≤ FGAIN 1 ≤ 4095 This register is only updated when the MSB (register 4Bh) is written to. This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-63. AFE Fine Gain for CVBS/Luma Subaddress Default 50h–51h 900h Subaddress 50h 51h 7 6 5 4 3 2 1 0 FGAIN 4 [7:0] Reserved FGAIN 4 [11:8] FGAIN 4 [11:0]: This fine gain applies to CVBS or S-Video luma (see AFE fine gain for Pb register) This register is only updated when the MSB (register 51h) is written to. This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-66. 3DNR Y Noise Sensitivity Subaddress Default 5Ah 80h 7 6 5 4 3 Y noise sensitivity[7:0] 2 1 0 1 0 1 0 1 0 1 0 1 0 Table 3-67. 3DNR UV Noise Sensitivity Subaddress Default 5Bh 80h 7 6 5 4 3 UV noise sensitivity[7:0] 2 Table 3-68. 3DNR Y Coring Threshold Limit Subaddress Default 5Ch 80h 7 6 5 4 3 Y coring threshold [7:0] 2 Table 3-69.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-73. " Blue" Screen Cr Control Subaddress Default 61h 80h 7 6 5 4 3 2 1 0 Cr value [9:2] The Cr value of the color screen output when enabled by bit 2 or 3 of the output formatter 2 register is programmable using a 10-bit value. The 8 MSB, bits[9:2], are represented in this register. The remaining two LSB are found in the "Blue" screen LSB register. The default color screen output is black. Table 3-74.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-78. F- and V-Bit Decode Control Subaddress Default 69h 00h 7 6 5 4 VPLL 3 Adaptive 2 Reserved 1 0 F-Mode[1:0] This register only works in manual gain control mode. When AGC is active, writing to any value is ignored.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-79. Back-End AGC Control Subaddress Default 6Ch 08h 7 6 5 4 Reserved 3 1 2 Peak 1 Color 0 Sync This register allows disabling the back-end AGC when the front-end AGC uses specific amplitude references (sync height, color burst, or composite peak) to decrement the front-end gain.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-83.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-85. AGC Increment Speed Subaddress Default 78h 06h 7 6 5 Reserved 4 3 2 1 AGC increment speed [2:0] 0 1 0 AGC increment speed: Adjusts gain increment speed. 111 = 7 (slowest) 110 = 6 (default) ⋮ 000 = 0 (fastest) Table 3-86.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-90. RAM Version LSB Subaddress 82h Read only 7 6 5 4 3 RAM version LSB [7:0] 2 1 0 1 0 1 0 RAM version LSB [7:0]: This register identifies the LSB of the RAM code revision number. Example: Patch Release = v04.04.02 ROM Version = 04h RAM Version MSB = 04h RAM Version LSB = 02h Table 3-91. Color PLL Speed Control Subaddress Default 83h 09h 7 6 5 4 3 2 Speed[3:0] Color PLL speed control. Table 3-92.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-95. 3DYC Luma Gain Subaddress Default 87h 08h/08h 7 6 5 4 3 3DYC luma gain [7:0] 2 1 0 This register contains a 5.3 format gain value used to calculate the luma difference value for luma coring. The gain can vary from 0 to 31.875 in steps of 0.125. The minimum value of 0 favors the 3D comb filter output, whereas the maximum value of 31.875 favors the 2D comb filter output. Table 3-96.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-99. IF Compensation Control Subaddress Default 8Dh 00h 7 6 5 4 3 U Reserved 2 V 1 Comp. 0 IF Enable Comp: 0 = Crosstalk compensation only. Use if SAW IF stage used. 1 = Crosstalk and low-frequency gain compensation. Use if non-SAW IF stage used.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-104. Weak Signal High Threshold Subaddress Default 96h 50h 7 6 5 4 3 2 1 0 Level [7:0] This register controls the lower threshold of the noise measurement that determines whether the input signal is considered a weak signal. Table 3-105.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-109. AGC Decrement Delay Subaddress Default 9Eh 1Eh 7 6 5 4 3 AGC decrement delay [7:0] 2 1 0 AGC decrement delay: Number of frames to delay gain decrements 1111 1111 = 255 0001 1110 = 30 (default) 0000 0000 = 0 Table 3-110.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-111.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 1P1[3] D1[3] 1M1[3] 1P1[2] D1[2] 1M1[2] 1P1[1] D1[1] 1M1[1] 1P1[0] D1[0] 1M1[0] NIBBLE 1 D2[3:0] NIBBLE 2 1P2[3:0] 1M2[3:0] PASS 1 D3[3:0] 1P3[3:0] Filter 1 Enable NIBBLE 3 00 1M3[3:0] D4[3:0] 01 NIBBLE 4 1P4[3:0] PASS 1M4[3:0] 10 D5[3:0] 1P5[3:0] NIBBLE 5 11 1M5[3:0] 2 Filter Logic FILTER 1 D1..D5 PASS 2 FILTER 2 2P1..2P5 2M1..2M5 Filter 2 Enable Figure 3-1. Teletext Filter Function Table 3-112.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-113. VDP FIFO Interrupt Threshold Subaddress Default BDh 80h 7 6 5 4 3 2 1 0 2 1 0 FIFO reset Thresh [7:0] Threshold [7:0]: This register is programmed to trigger an interrupt when the number of words in the FIFO exceeds this value. Note: 1 word equals 2 bytes. Table 3-114.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-117. VDP Pixel Alignment Subaddress Default C2h–C3h 01Eh Subaddress C2h C3h 7 6 5 4 3 Pixel alignment [7:0] 2 1 Reserved 0 Pixel alignment [9:0] Pixel alignment [9:0]: These registers form a 10-bit horizontal pixel position from the falling edge of horizontal sync, where the VDP controller will initiate the program from one line standard to the next line standard.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-122. VDP Full Field Mode Subaddress Default DAh FFh 7 6 5 4 3 Full field mode [7:0] 2 1 0 Full field mode [7:0]: This register programs the specific VBI standard for full field mode. It can be any VBI standard. Individual line settings take priority over the full field register. This allows each VBI line to be programmed independently but have the remaining lines in full field mode.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-127. VBUS Address Subaddress Default Subaddress E8h E9h EAh E8h 00h 7 6 E9h 00h 5 EAh 00h 4 3 VBUS address [7:0] VBUS address [15:8] VBUS address [23:16] 2 1 0 1 CC F1 0 Line VBUS address [23:0]: VBUS is a 24-bit wide internal bus. The user must program the 24-bit address of the internal register to be accessed via host port indirect access mode. Table 3-128.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-129. Interrupt Raw Status 1 Subaddress 7 F1h Read only 6 5 4 Reserved 3 2 1 0 FIFO full FIFO full: 0 = FIFO not full 1 = FIFO was full during write to FIFO The masked or unmasked status is set in the interrupt mask 1 register at subaddress F5h. The FIFO full error flag is set when the current line of VBI data can not enter the FIFO.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-131. Interrupt Status 1 Subaddress 7 F3h Read only 6 5 4 Reserved 3 2 1 0 FIFO full 2 CC F2 1 CC F1 0 Line FIFO full: Masked status of FIFO 0 = FIFO not full 1 = FIFO was full during write to FIFO, see the interrupt mask 1 register at subaddress F5h The masked or unmasked status is set in the interrupt mask 1 register. Table 3-132.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-134.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 3.2 www.ti.com VBUS Register Definitions Table 3-136. VDP Closed Caption Data Subaddress 80 051Ch – 80 051Fh Read only Subaddress 80 051Ch 80 051Dh 80 051Eh 80 051Fh 7 6 5 4 Closed Caption Closed Caption Closed Caption Closed Caption Field Field Field Field 3 1 byte 1 byte 2 byte 2 byte 2 1 0 1 2 1 2 These registers contain the closed caption data arranged in bytes per field. Table 3-137.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-138. VDP VITC Data Subaddress Subaddress 80 052Ch 80 052Dh 80 052Eh 80 052Fh 80 0530h 80 0531h 80 0532h 80 0533h 80 0534h 80 052Ch – 80 0534h Read only 7 6 5 4 3 VITC frame byte 1 VITC frame byte 2 VITC seconds byte 1 VITC seconds byte 2 VITC minutes byte 1 VITC minutes byte 2 VITC hours byte 1 VITC hours byte 2 VITC CRC byte 2 1 0 These registers contain the VITC data. Table 3-139.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-141. VDP V-Chip TV Rating Block 3 Subaddress 7 None 80 0542h Read only 6 TV-MA 5 TV-14 4 TV-PG 3 TV-G 2 TV-Y7 1 TV-Y 0 None TV Parental Guidelines Rating Block 1 None: No block intended TV-MA: When incoming video program is "TV-MA" rated in TV Parental Guidelines Rating, this bit is set high. TV-14: When incoming video program is "TV-14" rated in TV Parental Guidelines Rating, this bit is set high.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-143.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-144.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-145. Analog Output Control 2 Subaddress Default A0 005Eh B2h 7 6 5 4 3 2 Reserved 1 0 Gain[3:0] Analog output PGA gain [3:0]: These bits are effective when analog output AGC is disabled. Gain[3:0] 0000 1.30 0001 1.56 0010 (default) 1.82 0011 2.08 0100 2.34 0101 2.60 0110 2.86 0111 3.12 1000 3.38 1001 3.64 1010 3.90 1011 4.16 1100 4.42 1101 4.68 1110 4.94 1111 5.20 Table 3-146.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com Table 3-148.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 4 Typical Application Circuit 4.1 Typical Application Circuit Figure 4-1. Application Example Typical Application Circuit Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 5 www.ti.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 6 Electrical Specifications 6.1 Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) IOVDD to IOGND DVDD to DGND A33VDD (2) to (3) Supply voltage range A33GND A18VDD (4) to (5) A18GND MIN MAX UNIT 0.5 4.0 V –0.2 2.0 V –0.3 3.6 V –0.2 2.0 V VI to DGND Digital input voltage range –0.5 4.5 V VO to DGND Digital output voltage range –0.5 4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 6.3 www.ti.com Crystal Specifications CYSTAL SPECIFICATION MIN Frequency Frequency tolerance (1) NOM MAX 14.31818 (1) –50 UNIT MHz 50 ppm This number is the required specification for the external crystal/oscillator and is not tested. 6.4 DC Electrical Characteristics For minimum/maximum values: IOVDD = 3.0 V to 3.6 V, DVDD = 1.65 V to 1.95 V, AVDD33 = 3.0 V to 3.6 V, AVDD18 = 1.65 V to 1.95 V, TA = 0°C to 70°C.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 6.5 Analog Processing and A/D Converters FS = 60 MSPS for CH1, CH2 PARAMETER TEST CONDITIONS Zi Input impedance, analog video inputs specified by design (not tested) Ci Input capacitance, analog video inputs specified by design (not tested) Vi(PP) Input voltage range Ccoupling = 0.1 µF ΔG Input gain control range MIN TYP MAX UNIT 200 kΩ pF 0.50 1.0 V –6.7 Input gain ratio, N = 0 to 15 –7.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 6.7 www.ti.com I2C Host Port Timing PARAMETER TEST CONDITIONS MIN TYP MAX UNIT µs t1 Bus free time between STOP and START 1.3 t2 Data hold time t3 Data setup time 100 ns t4 Setup time for a (repeated) START condition 0.6 µs t5 Setup time for a STOP condition 0.6 µs t6 Hold time (repeated) START condition 0.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 6.8 SDRAM Timing (1) CL = 10 pF, CAS latency = 3, Clock delay = 0 ns PARAMETER TEST CONDITIONS MIN TYP MAX UNIT t1 Clock period (108 MHz) 9.2 ns t2 Clock high period 4.6 ns t3 Clock low period 4.6 t4 Clock to output valid time (address/data/control) t5 Output hold time 1.8 ns t6 Data in setup time 1.1 ns t7 Data in hold time 0.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 6.9 www.ti.com Example SDRAM Timing Alignment Samsung K4S161622E-80, CAS latency = 3, Clock delay = 0 ns t1 = 9.2 ns t6 = 1.1 ns t2 = 4.6 ns t7 = 0.3 ns 2.5 ns SDRAM_CLK Address/Data_out Data_in 9.2 ns 6 ns 2.5 ns 1 ns 4.6 ns 2.5 ns 1 ns 2 ns SDRAM_CLK_out Address/Data_in Data_out SDRAM-K4S161622E-80 (CAS LAT = 3) t(dsum) t(dhm) Data = read margin t(dsum) = 9.2 - 6 - 1.1 ns = 2.1 ns t(dhm) = 2.5 - 0.3 ns = 2.2 ns Figure 6-4.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 6.10 Memories Tested Table 6-1.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 7 www.ti.com Designing With PowerPAD™ The TVP5160 device is housed in a high-performance, thermally enhanced, 128-pin PowerPAD package (TI package designator: 128PFP). Use of the PowerPAD package does not require any special considerations except to note that the PowerPAD, which is an exposed die pad on the bottom of the device, is a metallic thermal and electrical conductor.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 www.ti.com 96 65 64 97 Exposed Thermal Pad 9,70 7,88 33 128 1 32 9,70 7,88 Top View NOTE: All linear dimensions are in millimeters Figure 7-1. 128-Pin PowerPAD Package Designing With PowerPAD™ Copyright © 2005–2011, Texas Instruments Incorporated Submit Documentation Feedback focus.ti.
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TVP5160 SLES135E – FEBRUARY 2005 – REVISED APRIL 2011 8 www.ti.com Revision History Table 8-1. Revision History REVISION SLES135 SLES135A COMMENTS Initial release Unknown Section 1.4, Related Products section added. Section 1.5, Trademarks modified. Table 1-1, I/O type modified for SCL pin. Table 2-1, Specified Y/C separation support by video standard. Figure 2-4, Crystal parallel resistor recommendation added. Table 2-9, CGMS support added for PAL. Table 2-11, Signal names modified.
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PACKAGE OPTION ADDENDUM www.ti.com 30-Aug-2013 PACKAGING INFORMATION Orderable Device Status (1) TVP5160PNP NRND Package Type Package Pins Package Drawing Qty HTQFP PNP 128 90 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Device Marking (3) CU NIPDAU Level-3-260C-168 HR (4/5) 0 to 70 TVP5160 (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
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