Datasheet

90%
Y, C, AVID,
VS, HS, FID
Valid DataValid Data
SCLK
t
1
t
2
t
6
t
5
t
3
t
4
10%
90%
10%
VC1 (SDA)
t
1
t
6
t
7
t
2
t
8
t
3
t
4
t
6
VC0 (SCL)
Data
Stop Start Stop
t
5
Change
Data
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011 www.ti.com
6.7 I
2
C Host Port Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Bus free time between STOP and START 1.3 µs
t
2
Data hold time 0 0.9 µs
t
3
Data setup time 100 ns
t
4
Setup time for a (repeated) START condition 0.6 µs
t
5
Setup time for a STOP condition 0.6 µs
t
6
Hold time (repeated) START condition 0.6 µs
t
7
Rise time VC1(SDA) and VC0(SCL) signal specified by design
(1)
250 ns
t
8
Fall time VC1(SDA) and VC0(SCL) signal specified by design
(1)
250 ns
C
b
Capacitive load for each bus line specified by design
(1)
400 pF
f
12C
I
2
C clock frequency 400 kHz
(1) Assured by design. Not tested.
Figure 6-1. Clocks, Video Data, and Sync Timing
Figure 6-2. I
2
C Host Port Timing
100 Electrical Specifications Copyright © 2005–2011, Texas Instruments Incorporated
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