Datasheet

SDRAM_CLK
t
5
Address/Control
Data_out
Data_in
t
2
t
1
t
3
t
4
t
7
t
6
TVP5160
www.ti.com SLES135E–FEBRUARY 2005–REVISED APRIL 2011
6.8 SDRAM Timing
(1)
C
L
= 10 pF, CAS latency = 3, Clock delay = 0 ns
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
t
1
Clock period (108 MHz) 9.2 ns
t
2
Clock high period 4.6 ns
t
3
Clock low period 4.6 ns
t
4
Clock to output valid time (address/data/control) 5.3 ns
t
5
Output hold time 1.8 ns
t
6
Data in setup time 1.1 ns
t
7
Data in hold time 0.3 ns
t
8
Clock rise time, 10% to 90% 4 ns
tg Clock fall time, 90% to 10% 4 ns
(1) Assured by design. Not tested.
Figure 6-3. SDRAM Interface Timing
Copyright © 2005–2011, Texas Instruments Incorporated Electrical Specifications 101
Submit Documentation Feedback
focus.ti.com: TVP5160