Datasheet

t = 4.6 ns
2
t = 9.2 ns
1
Address/Data_out
Data_in
SDRAM_CLK_out
Address/Data_in
Data_out
SDRAM_CLK
2 ns
1 ns
2.5 ns
t = 0.3 ns
7
t = 1.1 ns
6
9.2 ns
4.6 ns
6 ns
2.5 ns 2.5 ns
1 ns
t
(dhm)
t
(dsum)
Data = read margin
t = 9.2 - 6 - 1.1 ns = 2.1 ns
(dsum)
t = 2.5 - 0.3 ns = 2.2 ns
(dhm)
SDRAM-K4S161622E-80 (CAS LAT = 3)
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011 www.ti.com
6.9 Example SDRAM Timing Alignment
Samsung K4S161622E-80, CAS latency = 3, Clock delay = 0 ns
Figure 6-4. TVP5160 Timing Relationship with K4S161622E-80 SDRAM
102 Electrical Specifications Copyright © 2005–2011, Texas Instruments Incorporated
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