Datasheet
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
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Table 1-1. Terminal Functions (continued)
PIN
I/O DESCRIPTION
NAME NO.
Power Supplies
A33GND 1, 26, 27, P Analog 3.3-V return. Connect to analog ground.
28, 126, 128
A33VDD 2, 25, 125 P Analog power. Connect to analog 3.3-V supply.
A18GND 12, 14, 15 P Analog 1.8-V return. Connect to analog ground.
A18VDD 11, 13, 16 P Analog power. Connect to analog 1.8-V supply.
PLL18GND 124 P Analog power return. Connect to analog ground.
PLL18VDD 123 P Analog power. Connect to analog 1.8-V supply.
DGND 29, 34, 48,66, P Digital return. Connect to digital ground.
86, 100,112,
120
DVDD 33, 47, 65,85, P Digital core power. Connect to 1.8-V supply.
99, 111
IOGND 38, 58, 75,93, P Digital power return. Connect to digital ground.
106
IOVDD 37, 57, 74,92, P Digital I/O power. Connect to digital 3.3-V supply.
105
Sync Signals
HS / CS / 117 I/O Horizontal sync output or digital composite sync output
GPIO Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
VS / VBLK / 118 I/O Vertical sync output. (for modes with dedicated VS) or vertical blanking output
GPIO Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
FID / GPIO 116 I/O
Odd/even field indicator
Programmable general purpose I/O This pin must be pulled low through a 10-kΩ resistor for
correct device operation.
AVID / GPIO 115 I/O Active video indicator
Programmable general purpose I/O
Unused GPIO pins must be either configured as outputs, or tied to either IOVDD or DGND
SDRAM Interface
Address[11:0] 61, 77, O SDRAM address bus
62–64,
67–69, 81–78
D[15:0] 49–56, 46–39 I/O SDRAM data bus
WE 70 O SDRAM write enable
CAS 71 O SDRAM CAS enable
RAS 72 O SDRAM RAS enable
DQM 59 O SDRAM input/output mask for data
BA[1:0] 76, 73 O SDRAM bank address
SDRAM_CLK 60 O SDRAM 108-MHz clock
16 Introduction Copyright © 2005–2011, Texas Instruments Incorporated
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