Datasheet

Y[9:0] Cb
SCLK
EAV
1
Y Cr Y
EAV
2
EAV
3
EAV
4
SAV
1
SAV
2
SAV
3
SAV
4
Cb0 Y0 Cr0 Y1
0
HS Start
Horizontal Blanking
HS
HS Stop
A C
B
AVID
D
AVID Stop AVID Start
TVP5160
www.ti.com SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Figure 2-9. Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode
SCLK = 2× PIXEL CLOCK
(1)
MODE A B C D
NTSC 601 106 128 42 276
PAL 601 112 128 48 288
480p 106 128 42 276
576p 112 128 48 288
(1) ITU-R BT.656 10-bit 4:2:2 timing with 2× pixel clock reference 601 = ITU-R BT.601 timing
Copyright © 2005–2011, Texas Instruments Incorporated Functional Description 29
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