Datasheet

TVP5160
SLES135EFEBRUARY 2005REVISED APRIL 2011
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3 Internal Control Registers
The TVP5160 decoder is initialized and controlled by a set of internal registers that define the operating
parameters of the entire device. Communication between the external controller and the TVP5160
decoder is through a standard I
2
C host port interface, as described earlier.
Table 3-1 shows the summary of these registers. Detailed programming information for each register is
described in the following sections. Additional registers are accessible through an indirect procedure
involving access to an internal 24-bit address wide VBUS. Table 3-2 shows the summary of VBUS
registers.
Table 3-1. I
2
C Registers Summary
REGISTER NAME I
2
C SUBADDRESS DEFAULT R/W
(1)
Input/Output Select 00h 00h R/W
AFE Gain Control 01h 0Fh R/W
Video Standard Select 02h 00h R/W
Operation Mode 03h 00h R/W
Autoswitch Mask 04h 23h R/W
Color Killer 05h 10h R/W
Luminance Processing Control 1 06h 00h R/W
Luminance Processing Control 2 07h 00h R/W
Luminance Processing Control 3 08h 00h R/W
Luminance Brightness 09h 80h R/W
Luminance Contrast 0Ah 80h R/W
Chrominance Saturation 0Bh 80h R/W
Chroma Hue 0Ch 00h R/W
Chrominance Processing Control 1 0Dh 00h R/W
Chrominance Processing Control 2 0Eh 0Ch R/W
Reserved
(2)
0Fh
Pr Contrast 10h 80h R/W
Y Contrast 11h 80h R/W
Pb Contrast 12h 80h R/W
Reserved
(2)
13h
G/Y Brightness 14h 80h R/W
Reserved
(2)
15h
AVID Start Pixel 16h17h 55h/5Fh R/W
AVID Stop Pixel 18h19h 325h/32Fh R/W
HS Start Pixel 1Ah1Bh 00h/07h R/W
HS Stop Pixel 1Ch1Dh 40h/47h R/W
VS Start Line 1Eh1Fh 004h/001h R/W
VS Stop Line 20h21h 007h/004h R/W
VBLK Start Line 22h23h 001h/26Fh R/W
VBLK Stop Line 24h25h 015h/018h R/W
Embedded Sync Offset Control 1 26h 00h R/W
Embedded Sync Offset Control 2 27h 00h R/W
Fast Switch Control 28h C0h R/W
Fast Switch Overlay Delay 29h 17h R/W
Fast Switch SCART Delay 2Ah 1Ch R/W
Overlay Delay 2Bh 12h R/W
(1) R = Read only, W = Write only, R/W = Read and write
(2) Reserved I
2
C register addresses must not be written to.
38 Internal Control Registers Copyright © 20052011, Texas Instruments Incorporated
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