Datasheet
TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011
www.ti.com
List of Figures
1-1 TVP5160 PNP-Package Terminal Diagram .................................................................................. 15
2-1 Analog Processors and A/D Converters ...................................................................................... 18
2-2 Luminance Edge-Enhancer Peaking Block ................................................................................... 21
2-3 Peaking Filter Frequency Response NTSC/PAL ITU_R BT.601 Sampling............................................... 21
2-4 Reference Clock Configuration................................................................................................. 22
2-5 RTC Timing ....................................................................................................................... 23
2-6 Fast-Switches for SCART and Digital Overlay ............................................................................... 25
2-7 Vertical Synchronization Signals for 525-Line System ...................................................................... 28
2-8 Vertical Synchronization Signals for 625-Line System ...................................................................... 28
2-9 Horizontal Synchronization Signals for 10-Bit 4:2:2 Mode.................................................................. 29
2-10 Horizontal Synchronization Signals for 20-Bit 4:2:2 Mode.................................................................. 30
2-11 VS Position With Respect to HS for Interlaced Signals ..................................................................... 31
2-12 VS Position With Respect to HS for Progressive Signals................................................................... 31
2-13 VBUS Access ..................................................................................................................... 33
2-14 Reset Timing...................................................................................................................... 37
3-1 Teletext Filter Function .......................................................................................................... 80
4-1 Application Example ............................................................................................................. 95
6-1 Clocks, Video Data, and Sync Timing ....................................................................................... 100
6-2 I
2
C Host Port Timing............................................................................................................ 100
6-3 SDRAM Interface Timing ...................................................................................................... 101
6-4 TVP5160 Timing Relationship with K4S161622E-80 SDRAM............................................................ 102
7-1 128-Pin PowerPAD Package.................................................................................................. 105
4 List of Figures Copyright © 2005–2011, Texas Instruments Incorporated










