Datasheet

TVP5160
SLES135E–FEBRUARY 2005–REVISED APRIL 2011 www.ti.com
Table 3-2. VBUS Registers Summary
VBUS
REGISTER NAME SUBADDRESS DEFAULT R/W
(1)
Reserved
(2)(3)
00 0000h – 80 051Bh
VDP Closed Caption Data 80 051Ch – 80 051Fh R
VDP WSS/CGMS data 80 0520h – 80 0526h R
Reserved
(2)(3)
80 0527h – 80 052Bh
VDP VITC Data 80 052Ch – 80 0534h R
Reserved
(2)(3)
80 0535h – 80 053Fh
VDP V-Chip Data 80 0540h – 80 0543h R
Reserved
(2)(3)
80 0544h – 80 05FFh
VDP General Line Mode and Address 80 0600h – 80 0611h FFh, 00h R/W
Reserved
(2)(3)
80 0612h – 80 06FFh
VDP VPS/Gemstar EPG Data 80 0700h – 80 070Ch R
Reserved
(2)(3)
80 070Dh – A0 005Dh
Analog Output Control 2 A0 005Eh B2h R/W
Reserved
(2)(3)
A0 005Fh – B0 005Fh
Interrupt Configuration Register B0 0060h 00h R/W
Reserved
(2)(3)
B0 0062h – B0 0064h
Interrupt Mask 1 B0 0065h R
Interrupt Raw Status 1 B0 0069h R
Interrupt Status 1 B0 006Dh R
Interrupt Clear 1 B0 0071h R
Reserved
(2)(3)
B0 0073h – FF FFFFh
(1) R = Read only, W = Write only, R/W = Read and write
(2) Register addresses not shown in the register map summary are reserved and must not be written to.
(3) Writing to or reading from any value labeled "Reserved" register may cause erroneous operation of the TVP5160 decoder. For registers
with reserved bits, a 0b must be written to reserved bit locations unless otherwise stated.
42 Internal Control Registers Copyright © 2005–2011, Texas Instruments Incorporated
Submit Documentation Feedback
focus.ti.com: TVP5160