Datasheet

TVP5160
www.ti.com SLES135E–FEBRUARY 2005–REVISED APRIL 2011
Table 3-113. VDP FIFO Interrupt Threshold
Subaddress BDh
Default 80h
7 6 5 4 3 2 1 0
Thresh [7:0]
Threshold [7:0]: This register is programmed to trigger an interrupt when the number of
words in the FIFO exceeds this value.
Note: 1 word equals 2 bytes.
Table 3-114. VDP FIFO Reset
Subaddress BFh
Default 00h
7 6 5 4 3 2 1 0
Reserved FIFO reset
FIFO reset: Writing any data to this register clears the FIFO and VDP data registers. After clearing, this register bit is automatically cleared.
Table 3-115. VDP FIFO Output Control
Subaddress C0h
Default 00h
7 6 5 4 3 2 1 0
Reserved Host access
enable
Host access enable: This register is programmed to allow the host port access to the FIFO or allowing all VDP data to go out the video
output.
0 = Output FIFO data to the video output Y[9:2] (default)
1 = Allow host port access to the FIFO data
Table 3-116. VDP Line Number Interrupt
Subaddress C1h
Default 00h
7 6 5 4 3 2 1 0
Field 1 enable Field 2 enable Line number [5:0]
Field 1 interrupt enable:
0 = Disabled (default)
1 = Enabled
Field 2 interrupt enable:
0 = Disabled (default)
1 = Enabled
Line number [5:0]: Interrupt line number (default 00h)
This register is programmed to trigger an interrupt when the video line number exceeds this value in bits [5:0]. This interrupt must be
enabled at address F4h.
Note: The line number value of zero or one is invalid and will not generate an interrupt.
Copyright © 2005–2011, Texas Instruments Incorporated Internal Control Registers 81
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