Datasheet

TVP5160
www.ti.com SLES135E–FEBRUARY 2005–REVISED APRIL 2011
6.5 Analog Processing and A/D Converters
F
S
= 60 MSPS for CH1, CH2
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Z
i
Input impedance, analog video inputs specified by design (not tested) 200 kΩ
C
i
Input capacitance, analog video inputs specified by design (not tested) pF
V
i(PP)
Input voltage range C
coupling
= 0.1 µF 0.50 1.0 V
ΔG Input gain control range –6.7 dB
Input gain ratio, N = 0 to 15 –7.5% 0.5 +N/10
Input offset control per step 2 4 LSB
DNL Absolute differential nonlinearity AFE only 0.75 LSB
INL Absolute integral nonlinearity AFE only 1 LSB
FR Frequency response Multiburst (60 IRE) –0.9 dB
XTALK Crosstalk 1 MHz dB
SNR Signal-to-noise ratio all channels F
IN
= 1 MHz, 1.0 V
PP
54 dB
GM Gain match
(1)
Full scale, 1 MHz 1.5 %
Luma ramp
NS Noise spectrum –58 dB
(100 kHz to full, tilt null)
DP Differential phase Modulated ramp 0.5 °
DG Differential gain Modulated ramp ±1.5 %
Analog output gain ratio, N = 0 to 15 –8% 1.3 + 0.26xN 8 %
(1) Component inputs only
6.6 Data Clock, Video Data, Sync Timing
PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
Duty cycle SCLK 45 50 55 %
t
1
High time, SCLK @ 13.5 MHz ≥ 50% 37 ns
t
1
High time, SCLK @ 27 MHz ≥ 50% 18.5
t
1
High time, SCLK @ 54 MHz ≥ 50% 9.25
t
2
Low time, SCLK @ 13.5 MHz ≤ 50% 37 ns
t
2
Low time, SCLK @ 27 MHz ≤ 50% 18.5
t
2
Low time, SCLK @ 54 MHz ≤ 50% 9.25
t
3
Fall time, SCLK 90% to 10% 5 ns
t
4
Rise time, SCLK 10% to 90% 5 ns
t
5
Data valid time To 90%/10% 5 ns
t
6
Data hold time To 90%/10% 2.5 ns
Copyright © 2005–2011, Texas Instruments Incorporated Electrical Specifications 99
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