Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLinear ICsLinear IC - Video editing Video digitiser HTQFP 100 (14x14)

www.ti.com

FEATURES APPLICATIONS

DESCRIPTION

TVP7001

SLES164 – FEBBRUARY 2006

TRIPLE 8/10-BIT, 165/110 MSPS, VIDEO

AND GRAPHICS DIGITIZER WITH ANALOG PLL

• LCD TV/Monitors/Projectors

• Analog Channels

• DLP TV/Projectors

– -6 dB to 6 dB Analog Gain

• PDP TV/Monitors

– Analog Input MUXs

• PCTV Set-Top Boxes

– Auto Video Clamp

• Digital Image Processing

– Three Digitizing Channels, Each With

• Video Capture/Video Editing

Independently Controllable Clamp, PGA,

• Scan Rate/Image Resolution Converters

and ADC

• Video Conferencing

– Clamping: Selectable Clamping Between

• Video/Graphics Digitizing Equipment

Bottom Level and Mid-level

– Offset: 1024-Step Programmable RGB or

YPbPr Offset Control

TVP7001 is a complete solution for digitizing video

– PGA: 8-Bit Programmable Gain Amplifier

and graphic signals in RGB or YPbPr color spaces.

– ADC: 8/10-Bit 165/110 MSPS A/D Converter

The device supports pixel rates up to 165 MHz.

– Automatic Level Control Circuit

Therefore, it can be used for PC graphics digitizing

up to the VESA standard of UXGA (1600 × 1200)

– Composite Sync: Integrated Sync-on-Green

resolution at 60 Hz screen refresh rate, and in video

Extraction From GreenLuminance Channel

environments for the digitizing of digital TV formats,

– Support for DC and AC-Coupled Input

including HDTV up to 1080p. TVP7001 can be used

Signals

to digitize CVBS and S-video signal with 10-bit ADCs.

• PLL

The TVP7001 is powered from 3.3-V and 1.8-V

– Fully Integrated Analog PLL for Pixel Clock

supply and integrates a triple high-performance A/D

Generation

converter with clamping functions and variable gain,

independently programmable for each channel. The

– 12-165 MHz Pixel Clock Generation From

clamping timing window is provided by an external

HSYNC Input

pulse or can be generated internally. The TVP7001

– Adjustable PLL Loop Bandwidth for

includes analog slicing circuitry on the Y or G input to

Minimum Jitter

support sync-on-luminance or sync-on-green

– 5-Bit Programmable Subpixel Accurate

extraction. In addition, TVP7001 can extract discrete

Positioning of Sampling Phase

HSYNC and VSYNC from composite sync using a

sync slicer.

• Output Formatter

– Support for RGB/YCbCr 4:4:4 and YCbCr TVP7001 also contains a complete analog PLL block

to generate a pixel clock from the HSYNC input. Pixel

4:2:2 Output Modes to Reduce Board Traces

clock output frequencies range from 12 MHz to 165

– Dedicated DATACLK Output for Easy

MHz.

Latching of Output Data

All programming of the part is done via an

• System

industry-standard I

C interface, which supports both

– Industry-Standard Normal/Fast I

C Interface

reading and writing of register settings. The TVP7001

With Register Readback Capability

is available in a space-saving TQFP 100-pin

– Space-Saving TQFP-100 Pin Package

PowerPAD package.

– Thermally-Enhanced PowerPAD™ Package

for Better Heat Dissipation

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

PAGE 1
TVP7001 www.ti.
PAGE 2
TVP7001 www.ti.
PAGE 3
TVP7001 www.ti.
PAGE 4
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 TERMINAL FUNCTIONS TERMINAL NAME NO.
PAGE 5
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 TERMINAL FUNCTIONS (continued) TERMINAL NAME NO. I/O DESCRIPTION VSYNC_A VSYNC_B 78 79 I I Vertical sync input A Vertical sync input B. Unused inputs can be connected to ground. HSYNC_A HSYNC_B 81 82 I I Horizontal Sync input A Horizontal Sync input B. Unused inputs can be connected to ground. SOGIN1 SOGIN2 SOGIN3 1 99 97 I I I Sync-on-green input 1 Sync-on-green input 2 Sync-on-green input 3.
PAGE 6
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 ELECTRICAL CHARACTERISTICS IOVDD = 3.3 V, DVDD = 1.8 V, PLL_A18VDD = 1.9 V, A18VDD = 1.9 V, A33VDD = 3.3 V, TA = 25°C PARAMETER TEST CONDITIONS MIN TYP (1) MAX (2) 60 60 mA UNIT POWER SUPPLY IA33VDD 3.3-V supply current 78.75 MHz IIOVDD 3.3-V supply current 78.75 MHz 32 78 mA IA18VDD 1.8-V supply current 78.75 MHz 225 225 mA IPLL_18VDD 1.8-V supply current 78.75 MHz 14 14 mA IDVDD 1.8-V supply current 78.
PAGE 7
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 ELECTRICAL CHARACTERISTICS IOVDD = 3.3 V, DVDD = 1.8 V±0.1, PLL_A18VDD = 1.9 V±0.1, A18VDD = 1.9 V±0.1, A33VDD = 3.3 V, TA = 0°C to 70°C (unless otherwise noted) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 1.0 2.0 Vpp ANALOG INTERFACE ZI Input voltage range By design Input impedance, analog video inputs By design 0.
PAGE 8
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 TIMING REQUIREMENTS TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT CLOCKS, VIDEO DATA, SYNC TIMING Duty cycle DATACLK 50% t1 DATACLK rise time 10% to 90% t2 DATACLK fall time 90% to 10% t3 Output delay time (1) 1 1 1.5 Measured with a load of 15 pF. t1 DATACLK t2 R, G, B, HSOUT Valid Data Valid Data t3 Figure 1. Clock, Video Data, and Sync Timing 8 Submit Documentation Feedback ns ns 3.
PAGE 9
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 TIMING REQUIREMENTS PARAMETER I2C TEST CONDITIONS MIN TYP MAX UNIT HOST PORT TIMING t1 Bus free time between STOP and START Specified by design 1.3 µs t2 Setup time for a (repeated) START condition Specified by design 0.6 µs t3 Hold time (repeated) START condition Specified by design 0.6 µs t4 Setup time for a STOP condition Specified by design 0.
PAGE 10
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 FUNCTIONAL DESCRIPTION Analog Channel The TVP7001 contains three identical analog channels that are independently programmable. Each channel consists of a clamping circuit, a programmable gain amplifier, automatic offset control and an A/D converter. Analog Input Switch Control TVP7001 has 3 analog channels that accept up to 10 video inputs. The user can configure the internal analog video switches via the I2C interface.
PAGE 11
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Analog PLL The analog PLL generates a high-frequency internal clock used by the ADC sampling and data clocking out to derive the pixel output frequency with programmable phase. The reference signal for this PLL is the horizontal sync signal supplied on the HSYNC input or from extracted horizontal sync of sync slicer block for embedded sync signals.
PAGE 12
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 89 PLL_F 4.7 nF 88 1.5 kΩ 87 0.1 µF FILT2 FILT1 TVP7000 Figure 4. PLL Loop Filter Table 1. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display Formats STANDAR D RESOL. REFRESH RATE HORIZ. FREQ. (kHz) PIXEL RATE (MHz) PLL Divider Total pix/line PLLDIV [11:4] Reg 01h [7:0] PLLDIV [3:0] Reg 02h [7:4] Reg 03h Output Divider Reg 04h [0] VCO RANGE Reg 03h [7:6] CP CURRENT Reg 03h [5:3] VGA 640 × 480 60 Hz 31.
PAGE 13
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Activity Detect SOGOUT SYNC Slicer SOG SYNC Separator Activity Detect 5MHz CLK HSYNC Activity Detect VSYNC VSOUT Polarity Detect COAST HSYNC Clock Generation HSOUT COAST DATACLK Phase Select DIV ADC Figure 5. Sync Processing Timing The TVP7001 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing diagrams are shown for operation with internal PLL clock at phase 0.
PAGE 14
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 RGBin P0 P1 P3 P10 P11 P12 HSYNC DATACLK 13 clocks latency D0 RGBout D1 D3 D4 D5 Programmable Width HSOUT 4:4:4: RGB/YCbCr Output Timing RGBin P0 P1 P3 P10 P11 P12 HSYNC DATACLK 13 clocks latency GOUT Y0 Y1 Y2 Y3 Y4 BOUT Cb0 Cr0 Cb2 Cr2 Cb4 HSOUT Programmable Width 4:2:2 YCbCr Output Timing Figure 6.
PAGE 15
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 2 I C Host Interface Communication with the TVP7001 device is via an I2C host interface. The I2C standard consists of two signals, serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multi-mastered, the TVP7001 can function as a slave device only.
PAGE 16
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Table 4. Reset Sequence SIGNAL NAME DURING RESET RESET COMPLETED ROUT[9:0], BOUT[9:0], BOUT[9:0] High impedance Output HSOUT, VSOUT, SOGOUT High impedance Output DATACLK High impedance Output 5 ms 1 µs 1 µs Power Reset I2C Figure 7. Reset Timing Control Registers The TVP7001 is initialized and controlled by a set of internal registers that define the operating parameters of the entire device.
PAGE 17
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Table 5.
PAGE 18
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 PLL Divide Subaddress 01h–02h 7 6 Default (69D0h) 5 4 3 2 1 0 PLL divide MSB [11:4] PLL divide LSB [3:0] Reserved PLL divide [11:0]: PLL divide number sets the number of pixels per line. Controls the PLL feedback divider.
PAGE 19
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 HSYNC Output Width Subaddress 07h 7 Default (20h) 6 5 4 3 2 1 0 HSOUT Width [7:0] HSOUT Width [7:0]: Sets the width in pixels for HSYNC output. Blue Fine Gain Subaddress 08h 7 Default (80h) 6 5 4 3 2 1 0 Blue Gain [7:0] Blue Gain [7:0]: PGA digital gain (contrast) for Blue channel applied after the ADC. Fine Gain = 1 + Blue Gain[7:0]/256 Blue Fine Gain 00h 80h FFh Fine Gain 1.0 1.5 (default) 2.
PAGE 20
TVP7001 www.ti.
PAGE 21
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Sync On_Green Threshold Subaddress 10h 7 Default (B8h) 6 5 4 3 SOG Threshold [4:0] 2 1 0 Blue CS Green CS Red CS SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator. The minimum setting is 0 mV and the maximum is 350 mV. The step is 11.2 mV.
PAGE 22
TVP7001 www.ti.
PAGE 23
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Test Register Subaddress 16h 7 Default (00h) 6 5 4 Pixel tolerance [2:0] 3 Reserved 2 Test output 1 0 PLL PD STRTB Pixel tolerance: Controls sensitivity to HSYNC input stability. Increasing the pixel tolerance may be required for input signals having horizontal instability.
PAGE 24
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Blue and Green Coarse Gain Subaddress 1Bh 7 Default (55h) 6 5 4 3 2 Green Gain [3:0] 1 0 Blue Gain [3:0] Green Coarse Gain [3:0]: Coarse analog gain for Green channel applied before the ADC. To avoid clipping at the ADC, Vp-p in X Gain must be less than 1 Vp-p. Gain [3:0] Description 0000 = 0.5 0001 = 0.6 0010 = 0.7 0011 = 0.8 0100 = 0.9 0101 = 1.0 0110 = 1.1 0111 = 1.2 1000 = 1.3 Maximum recommended gain for 700mVp-p input. 1001 = 1.4 1010 = 1.
PAGE 25
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Green Coarse Offset Subaddress 1Fh 7 Default (20h) 6 5 4 Reserved 3 2 1 0 Coarse Green offset [5:0] Green Coarse offset [5:0]: Coarse analog offset for green channel applied before the ADC. 1Fh = +124 LSB (Recommended for optimum ALC performance) Red Coarse Offset Subaddress 20h 7 Default (20h) 6 5 4 Reserved 3 2 1 0 Coarse Red offset [5:0] Red Coarse offset [5:0]: Coarse analog offset for blue channel applied before the ADC.
PAGE 26
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 Automatic Level Control Filter Subaddress 7 28h Default (00h) 6 Reserved 5 4 3 2 NSV[3:0] 1 0 NSH [2:0] The horizontal ALC coefficient (NSH) specifies the number of the horizontal samples (N) used to calculate the average blank level per horizontal line. Offset error correction is applied immediately based on the vertical (NSV) coefficient.
PAGE 27
TVP7001 www.ti.
PAGE 28
TVP7001 www.ti.
PAGE 29
TVP7001 www.ti.com SLES164 – FEBBRUARY 2006 APPLICATION INFORMATION 1.5 kΩ 4.7 nF 10 nF GIN1 FILT1 G/Y PLL_F SOG1 0.1 µF FILT2 0.1 µF 75 Ω GOUT[9:0] 0.1 µF B/Pb BOUT[9:0] BIN1 75 Ω ROUT[9:0] 0.1 µF R/Pr DATACLK RIN1 75 Ω TVP7001 SOGOUT HSYNC HSYNC_A VSOUT VSYNC VSYNC_A HSOUT TMS CLAMP I2C SCL SDA +3.3 V PWDN COAST RESETB 2.2 kΩ x 2 2.2 kΩ x 3 Figure 8.
PAGE 30
1 2 3 A3.3V 4 5 6 A1.8V I2C ADDRESS SELECTION 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 2-3: Base Addr 0xBA 0.1uF 1-2: Base Addr 0xB8 - Default D 1.5k D3.3V D1.8V 4.7nF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 0.1uF 10k 0.1uF FILT1 FILT2 PLL_F 3 0.1uF D D3.3V PLLA1.8V I2CA 2 1 JMP3 VSYNC_A VSYNC_B 10k HSYNC_A HSYNC_B PLL_F FILT2 FILT1 0.1uF EXT_CLK TP GIN_4 10nF 0.1uF 1 GIN_3 A3.3V PLLA1.8V 10nF GIN_2 0.1uF D1.8V D3.3V 2.2k (2) D3.
PAGE 31
PAGE 32
PAGE 33
PAGE 34
PAGE 35
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.