TVP7002 www.ti.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com The TVP7002 is powered from 3.3-V and 1.9-V supply and integrates a triple high-performance analog-to-digital (A/D) converter with clamping functions and variable gain, independently programmable for each channel. The clamp timing window is provided by an external pulse or can be generated internally. The TVP7002 includes analog slicing circuitry on the SOG inputs to support sync-on-luminance or sync-on-green extraction.
TVP7002 www.ti.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 1. Terminal Functions TERMINAL NAME NO.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Table 1. Terminal Functions (continued) TERMINAL NAME NO. I/O DESCRIPTION Power Supplies NSUB 21, 91 I Substrate ground. Connect to analog ground. A33VDD 13, 14, 93, 94 I Analog power. Connect to 3.3 V. A33GND 12, 15, 92, 95 I Analog 3.3-V return. Connect to ground. AGND 3, 5, 8, 20 I Analog 1.9-V return. Connect to ground. AVDD 4, 6, 7, 19 I Analog power. Connect to 1.9 V. PLL_AVDD 84, 85 I PLL analog power.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) IOVDD to IOGND –0.5 V to 4.5 V DVDD to DGND –0.5 V to 2.3 V PLL_AVDD to PLL_AGND and AVDD to AGND –0.5 V to 2.3 V A33VDD to A33GND –0.5 V to 4.5 V Digital input voltage range VI to DGND –0.5 V to 4.5 V Analog input voltage range AI to A33GND –0.2 V to 2.3 V Digital output voltage range VO to DGND –0.5 V to 4.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Electrical Characteristics IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 25°C TEST CONDITIONS (1) PARAMETER TYP (2) TYP (3) UNIT Power Supply IA33VDD 3.3-V supply current 78.75 MHz, BC = 5 67 67 mA IIOVDD 3.3-V supply current 78.75 MHz, BC = 5 21 56 mA IAVDD 1.9-V supply current 78.75 MHz, BC = 5 206 209 mA IPLL_VDD 1.9-V supply current 78.75 MHz, BC = 5 16 16 mA IDVDD 1.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Electrical Characteristics IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, TA = 0°C to 70°C (unless otherwise noted) TEST CONDITIONS (1) PARAMETER MIN TYP MAX 1 2 UNIT Analog Interface ZI Input voltage range By design Input impedance, analog video inputs By design 0.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Timing Requirements TEST CONDITIONS (1) PARAMETER MIN TYP MAX UNIT Positive duty cycle, DATACLK (CLK POL = 0) 48 50 52 % Positive duty cycle, DATACLK (CLK POL = 1) 41 43 45 % Clocks, Video Data, Sync Timing t1 DATACLK rise time 10% to 90% 1 t2 DATACLK fall time 90% to 10% 1 t3 (RGB data) RGB output delay time (1) 0 ns ns 1.5 ns Measured at 162 MHz with 22-Ω series termination resistor and 10-pF load.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Timing Requirements PARAMETER TEST CONDITIONS MIN TYP MAX UNIT I2C Host Port t1 Bus free time between Stop and Start Specified by design 1.3 μs t2 Setup time for a (repeated) Start condition Specified by design 0.6 μs t3 Hold time (repeated) Start condition Specified by design 0.6 μs t4 Setup time for a Stop condition Specified by design 0.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 FUNCTIONAL DESCRIPTION Analog Channel The TVP7002 contains three identical analog channels that are independently programmable. Each channel consists of a clamping circuit, programmable gain control, programmable offset control, and an ADC. Analog Input Switch Control TVP7002 has three analog channels that accept up to ten video inputs. The user can configure the internal analog video switches via the I2C interface.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com The selection between bottom- and mid-level clamping is performed by I2C subaddress 10h (see Sync-On-Green Threshold). The fine clamps must also be enabled via I2C register 2Ah for proper operation. The internal clamping time can be adjusted using the I2C clamp start and width registers at subaddress 05h and 06h, respectively (see Clamp Start and Clamp Width). Table 3.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Automatic Level Control (ALC) The ALC circuit maintains the level of the signal to be set at a value that is programmed at the fine offset I2C register. It consists of a pixel averaging filter and feedback loop. This ALC function can be enabled or disabled by the I2C register at subaddress 26h. The ALC circuit needs a timing pulse generated internally but the user should program the position properly.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com The purpose of the 2-bit VCO range control is to improve the noise performance of the TVP7002. The frequency ranges for the VCO are shown in Table 4. The phase of the ADC sample clock generated by the horizontal PLL can be accurately controlled in 32 uniform steps over a single clock period (360/32 = 11.25 degrees phase resolution) using the phase select register located at subaddress 04h.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Table 4. Recommended VCO Range and Charge Pump Current Settings for Supporting Standard Display Formats (continued) STANDARD RESOLUTION FRAME RATE (Hz) LINE RATE (kHz) PIXEL RATE (MHz) PLL DIVIDER TOTAL PIX/LINE PLLDIV [11:4] REG 01h [7:0] PLLDIV [3:0] REG 02h [7:4] REG 03h OUTPUT DIVIDER REG 04h [0] VCO RANGE REG 03h [7:6] CP CURRENT REG 03h [5:3] 720 × 480i 29.97 15.734 13.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Sync Slicer TVP7002 includes a circuit that compares the input signal on Green channel to a level 150 mV (typical value) above the clamped level (sync tip). The slicing level is programmable by I2C register subaddress at 10h. The digital output of the composite sync slicer is available on the SOGOUT pin. Noise Immunity In general, noise on a slowly varying input signal (i.e.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 If activity is not detected on either the HSYNC input or the VSYNC input, the host processor should assume that the PC graphics input is a standard 3-wire interface. With AHSO and AVSO set for automatic selection and no signals present at the HSYNC and VSYNC input pins, the TVP7002 will automatically select the SOG input as the sync source. Table 5.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Output Formatter The output formatter sets how the data is formatted for output on the TVP7002 output buses. Table 6 shows the available component video output modes. Table 6.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Embedded Syncs Standard embedded syncs insert SAV and EAV codes into the data stream on the rising and falling edges of AVID. These codes contain the V and F bits that also define vertical timing. Table 7 gives the format of the SAV and EAV codes. H = 1 always indicates EAV. H = 0 always indicates SAV. The alignment of V and F to the line and field counter varies depending on the standard.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Output Range Limits The TVP7002 provides selectable output range limits in I2C subaddress 15h: 00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default) 01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019) 10 = ITU-R BT.601 coding range (Y ranges from 64 to 940, Cb and Cr range from 64 to 960) 11 = Reserved NOTE RGB coding range not allowed with embedded syncs.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Timing The TVP7002 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing diagrams are shown for operation with internal PLL clock at phase 0 and HSOUT Output Start = 0. For the 4:2:2 mode, CbCr data output is on the BOUT[9:0] output port. 4:4:4 RGB Output Timing. RGB output latency (RGBPD) is 18 clock cycles. HSOUT latency (HSPD) is 5 clock cycles with HS Start set to 0. 4:2:2 YCbCr Output Timing.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 I2C Host Interface Communication with the TVP7002 device is via an I2C host interface. The I2C standard consists of two signals, serial input/output data (SDA) line and input clock line (SCL), which carry information between the devices connected to the bus. A third signal (I2CA) is used for slave address selection. Although an I2C system can be multi-mastered, the TVP7002 can function as a slave device only.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Power Up, Reset, and Initialization No specific power-up sequence is required, but all power supplies should be active and stable within 500 ms of each other. RESETB may be low during power up, but must remain low for at least 1 μs after the power supplies become stable. Alternatively, reset may be asserted any time with minimum 5-ms delay after power-up and must remain asserted for at least 1 μs. Reset timing is shown in Figure 7.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 CONTROL REGISTERS The TVP7002 is initialized and controlled by a set of internal registers that define the operating parameters of the entire device. Communication between the external controller and the TVP7002 is through a standard I2C host port interface, as previously described. Table 12 shows the summary of these registers. Detailed programming information for each register is described in the following sections. Table 12.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Table 12.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Register Definitions Chip Revision Subaddress 00h 7 Read Only 6 5 4 3 Chip revision [7:0] 2 1 0 Chip revision [7:0]: Chip revision number H-PLL Feedback Divider MSBs Subaddress 01h 7 Default (67h) 6 5 4 3 PLL divide [11:4] 2 1 0 PLL divide [11:0]: Controls the 12-bit horizontal PLL feedback divider value that determines the number of pixels per line. PLL divide [11:4] bits should be loaded first whenever a change is required.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com H-PLL Phase Select Subaddress 04h 7 Default (80h) 6 5 Phase Select [4:0] 4 3 2 1 Reserved 0 DIV2 Phase Select [4:0]: ADC sampling clock phase select. (1 LSB = 360/32 = 11.25°). A host-based automatic phase control algorithm can be used to control this setting to optimize graphics sampling phase. 00h = 0 degrees 10h = 180 degrees (default) 1Fh = 348.75 degrees DIV2: DATACLK divide-by-2. H-PLL post divider.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Green Fine Gain Subaddress 09h 7 Default (00h) 6 5 4 3 Green Fine Gain [7:0] 2 1 0 Green Fine Gain [7:0]: 8-bit fine digital gain (contrast) for Green channel (applied after the ADC). Offset binary value. Green Fine Gain = 1 + Green Fine Gain [7:0]/256 Green Fine Gain [7:0] Green Fine Gain 00h 1.0 (default) 80h 1.5 FFh 2.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Red Fine Offset MSBs Subaddress 0Dh 7 Default (80h) 6 5 4 3 Red Fine Offset [9:2] 2 1 0 Red Fine Offset [9:2]: 8 MSBs of 10-bit fine digital offset (brightness) for Red channel (applied after ADC). Corresponding two LSBs located at register 1Dh. Offset binary value. The default setting of 80h places the bottom-level (RGB) clamped output blank levels at 0 and mid-level clamped (PbPr) output blank levels at 512.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 H-PLL and Clamp Control Subaddress 7 CF 0Fh Default (2Eh) 6 CP 5 Coast Sel 4 CPO 3 CPC 2 SMO 1 FCPD 0 ADC Test CF: Clamp Function. Clamp pulse select. This control bit determines whether the timing for both the fine clamp and the ALC circuit are generated internally or externally. 0 = Internal fine clamp and ALC timing (default) 1 = External fine clamp and ALC timing (pin 76) CP: Clamp Polarity.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Sync-On-Green Threshold Subaddress 10h 7 Default (5Dh) 6 5 SOG Threshold [4:0] 4 3 2 Blue CS 1 Green CS 0 Red CS SOG Threshold [4:0]: Sets the voltage level of the SOG slicer comparator according to the following equation. slice_level = (350 mV) × (NTH/31) 00h = 0 mV 0Bh = 124 mV (default) 1Fh = 350 mV Blue Clamp Select: This bit has no effect when the Blue channel fine clamp is disabled (bit 2 of subaddress 2Ah).
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 H-PLL Post-Coast Subaddress 13h Default (00h) 7 6 5 4 3 2 1 0 Post-Coast [7:0] Post-Coast [7:0]: Sets the number of HSYNC periods that coast stays active following VSYNC trailing edge. Post-Coast settings must be extended to include Macrovision™ pseudo syncs when Macrovision is present. Table 14.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Output Formatter Subaddress 15h 7 Reserved Default (04h) 6 5 Output code range [1:0] 4 Reserved 3 Clamp REF 2 CbCr order 1 422/444 0 Sync En Reserved [7]: 0 = Required (default) Output code range [1:0]: 00 = RGB coding range (Y, Cb, and Cr range from 0 to 1023) (default) 01 = Extended coding range (Y, Cb, and Cr range from 4 to 1019) 10 = ITU-R BT.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 MISC Control 2 Subaddress 17h 7 Reserved Default (03h) 6 5 Test output control [2:0] 4 3 2 1 SOG En Reserved 0 Output En Test output control [2:0]: Selects which signal is output on pin 22. Output polarity control is also provided using bit 2 of subaddress 18h. 000 = Field ID output (default) 001 = Data Enable output 010 = Reserved 011 = Reserved 100 = Internal clock reference output (~6.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Input Mux Select 1 Subaddress 19h 7 6 SOG Select [1:0] Default (00h) 5 4 Red Select [1:0] 3 2 Green Select [1:0] 1 0 Blue Select [1:0] SOG Select [1:0]: Selects one of three SOG inputs. 00 = SOGIN_1 input selected (default) 01 = SOGIN_2 input selected 10 = SOGIN_3 input selected 11 = Reserved Red Select [1:0]: Selects one of three R/Pr inputs.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Input Mux Select 2 Subaddress 1Ah 7 6 SOG LPF SEL [1:0] Default (C2h) 5 4 CLP LPF SEL [1:0] 3 CLK SEL 2 VS SEL 1 PCLK SEL 0 HS SEL SOG LPF SEL [1:0]: SOG low-pass filter selection. The SOG low-pass filter can be used to attenuate glitches present on the SOG input. Excessive filtering can lead to sync detection issues and increased sample clock jitter. 00 = 2.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Blue and Green Coarse Gain Subaddress 1Bh 7 Default (77h) 6 5 Green Coarse Gain [3:0] 4 3 2 1 Blue Coarse Gain [3:0] 0 Green Coarse Gain [3:0]: 4-bit coarse analog gain for Green channel (applied before the ADC). To avoid clipping at the ADC, VP-P in X Gain must be less than 1 VP-P. Gain [3:0] Description 0000 = 0.5 0001 = 0.6 0010 = 0.7 0011 = 0.8 0100 = 0.9 0101 = 1.0 0110 = 1.1 0111 = 1.2 Default 1000 = 1.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Blue Coarse Offset Subaddress 1Eh 7 Default (10h) 6 5 4 Reserved 3 2 Blue Coarse Offset [5:0] 1 0 Blue Coarse Offset [5:0]: 6-bit coarse analog offset for Blue channel (applied before ADC). 6-bit sign magnitude value. Coarse Offset settings less than 10h can lead to bottom level clipping at the ADC input.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com MISC Control 4 Subaddress 22h 7 SP Reset Default (08h) 6 5 Yadj_delay [2:0] 4 3 MAC_EN 2 Coast Dis 1 VS Select 0 VS Bypass SP Reset: Active-high reset for Sync Processing block. This bit may be used to manually reset the sync separator, sync accumulator, activity and polarity detectors, and line and pixels counters.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Green Digital ALC Output LSBs Subaddress 24h 7 Read only 6 5 4 3 Green ALC Out [7:0] 2 1 0 Green ALC Out [7:0]: Eight LSBs of 10-bit filtered digital ALC output for Green channel. The corresponding two MSBs are located at subaddress 27h. Twos-complement value. Also see register 23h.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Automatic Level Control Filter Subaddress 28h 7 Reserved Default (53h) 6 5 4 3 2 NSV [3:0] 1 NSH [2:0] 0 NSV [3:0]: ALC vertical filter coefficient. First-order recursive filter coefficient. ALC updates once per video line. NSV [3:0] Description 0000 = 1 Fastest setting. ALC converges in one iteration (i.e.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Fine Clamp Control Subaddress 2Ah 7 CM Offset Default (07h) 6 5 Reserved 4 3 Fine swsel [1:0] 2 Reserved 1 Fine GB 0 Fine R CM Offset: Fine bottom-level clamp common mode offset enable. The common mode offset is approximately 300 mV when enabled. Has no effect when the coarse clamp or fine mid-level clamp is selected. See registers 10h and 2Dh.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com ADC Setup Subaddress 2Ch 7 (Default 50h) 6 5 ADC bias control [3:0] 4 3 2 1 0 Trim clamp [3:0] ADC bias control [3:0]: Allows adjusting the internal ADC bias current for optimum performance. 0h = Minimum setting 5h = Recommended setting for sample rates ≤ 110 MSPS (default) 8h = Recommended setting for sample rates > 110 MSPS Fh = Maximum setting Trim clamp [3:0]: SOG coarse clamp bias current control.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 RGB Coarse Clamp Control Subaddress 2Fh 7 (Default 8Ch) 6 5 4 3 2 RGB leakage [5:0] Reserved 1 0 RGB leakage [5:0]: RGB channel coarse clamp leakage current switch. Increasing the coarse clamp leakage current increases horizontal droop but improves hum rejection. 00h = 0.5 μA 0Ch = 6.5 μA when IBIAS = 2 μA (default) 3Fh = 32.0 μA when IBIAS = 2 μA Droop_Current = 0.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com Macrovision Stripper Width Subaddress 34h 7 Default (03h) 6 5 4 3 stripper width [7:0] 2 1 0 When the MAC_EN bit in Reg 22h is set to 1, this setting creates a stripper window around HSYNC for masking Macrovision pseudo-syncs or glitches that could affect PLL lock. The actual stripper width is determined from the stripper width [7:0] setting and can be approximated by 2 x stripper width [7:0] x REFCLK period.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 Lines Per Frame Status Subaddress 37h–38h Subaddress 37h 38h 7 6 5 Read only Reserved mac detect P/I detect 4 3 Lines per Frame [7:0] Reserved 2 1 0 Lines per Frame [11:8] mac detect: Macrovision pseudo-sync detection status 0 = Macrovision not detected 1 = Macrovision detected P/I detect: Progressive/interlaced video detection status. Not dependent on the H-PLL being locked.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com VSYNC Width Subaddress 3Ch 7 Read only 6 Reserved 5 4 3 2 VSYNC width [4:0] 1 0 VSYNC width [4:0]: Number of lines between the leading and trailing edges of the VSYNC input. The VSYNC width along with the HSYNC and VSYNC polarities can be used to determine whether the input graphics format is using VESA-CVT generated timings. NOTE: The VSYNC width counter is not dependent on the H-PLL being locked.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 AVID Stop Pixel Subaddress 42h–43h Subaddress 42h 43h 7 Default (062Ch) 6 5 4 3 AVID stop [7:0] Reserved 2 1 0 AVID stop [12:8] AVID stop [12:0]: AVID stop pixel number. The number of pixels of active video must be an even number. This is an absolute pixel location from the leading edge of HSYNC (start pixel 0). The TVP7002 updates the AVID Stop only when the AVID Stop MSB byte is written to.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com F-bit Field 1 Start Line Offset Subaddress 49h Default (00h) 7 6 5 4 3 F-bit start 1 [7:0] 2 1 0 F-bit start 1 [7:0]: F-bit Field 1 start line offset relative to the leading edge of VSYNC, signed integer, set F-bit to 1 until field 0 start line, it only applies in interlaced mode. For a non-interlace mode, F-Bit is always set to 0. NOTE: The field ID output (FIDOUT) is always aligned with the leading edge of the VSYNC output (VSOUT).
TVP7002 www.ti.
TVP7002 SLES206C – MAY 2007 – REVISED APRIL 2013 www.ti.com APPLICATION INFORMATION PLL Loop Filter 0.1 µF 4.7 nF 1 nF G/Y GIN_1 FILT1 FILT2 0.1 µF PLL_F SOGIN_1 1.5 kW 75 W G[9:0] 0.1 µF B/Pb B[9:0] BIN_1 75 W R[9:0] 0.1 µF R/Pr DATACLK RIN_1 75 W TVP7002 HSYNC FIDOUT HSYNC_A 330 W SOGOUT 5 V/3.3 V VSYNC VSOUT VSYNC_A 1 nF HSOUT TMS CLAMP PWDN COAST SCL SDA 3.3 V I2CA RESETB 2.2 kW × 2 2.
TVP7002 www.ti.com SLES206C – MAY 2007 – REVISED APRIL 2013 REVISION HISTORY Revision SLES206 Comments Initial Release SLES206A Changed Functional Block Diagram Updated Timing Requirements Changed Sync Activity Detection section Changed Power Up, Reset, and Initialization section Editorial changes throughout SLES206B Modified pin 73 I2CA pin description in Table 1, Terminal Functions. Reset and I2C Bus Address Selection section, Modified I2CA description and Table 10.
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