Datasheet

4:4:4 RGB Output Timing. RGB output latency (RGB ) is 18 clock cycles. HSOUT latency (HS ) is 5 clock cycles with HS Start set to 0.
PD PD
4:2:2 YCbCr Output Timing. YCbCr output latency (YC ) is 39 clock cycles. HSOUT latency (HS ) is 5 clock cycles with HS Start set to 0.
PD PD
TVP7002
SLES206C –MAY 2007–REVISED APRIL 2013 www.ti.com
Timing
The TVP7002 supports RGB/YCbCr 4:4:4 and YCbCr 4:2:2 modes. Output timing is shown in Figure 6. All timing
diagrams are shown for operation with internal PLL clock at phase 0 and HSOUT Output Start = 0. For the 4:2:2
mode, CbCr data output is on the BOUT[9:0] output port.
Figure 6. Output Timing Diagram
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