Datasheet
TVP7002
www.ti.com
SLES206C –MAY 2007–REVISED APRIL 2013
CONTROL REGISTERS
The TVP7002 is initialized and controlled by a set of internal registers that define the operating parameters of the
entire device. Communication between the external controller and the TVP7002 is through a standard I
2
C host
port interface, as previously described.
Table 12 shows the summary of these registers. Detailed programming information for each register is described
in the following sections.
Table 12. Control Registers Summary
(1) (2)
REGISTER NAME I
2
C SUBADDRESS DEFAULT R/W
(3)
Chip Revision 00h 02h R
H-PLL Feedback Divider MSBs 01h 67h R/W
H-PLL Feedback Divider LSBs 02h 20h R/W
H-PLL Control 03h A8h R/W
H-PLL Phase Select 04h 80h R/W
Clamp Start 05h 32h R/W
Clamp Width 06h 20h R/W
HSYNC Output Width 07h 20h R/W
Blue Fine Gain 08h 00h R/W
Green Fine Gain 09h 00h R/W
Red Fine Gain 0Ah 00h R/W
Blue Fine Offset MSBs 0Bh 80h R/W
Green Fine Offset MSBs 0Ch 80h R/W
Red Fine Offset MSBs 0Dh 80h R/W
Sync Control 1 0Eh 5Bh R/W
H-PLL and Clamp Control 0Fh 2Eh R/W
Sync On Green Threshold 10h 5Dh R/W
Sync Separator Threshold 11h 20h R/W
H-PLL Pre-Coast 12h 00h R/W
H-PLL Post-Coast 13h 00h R/W
Sync Detect Status 14h R
Output Formatter 15h 04h R/W
MISC Control 1 16h 11h R/W
MISC Control 2 17h 03h R/W
MISC Control 3 18h 00h R/W
Input Mux Select 1 19h 00h R/W
Input Mux Select 2 1Ah C2h R/W
Blue and Green Coarse Gain 1Bh 77h R/W
Red Coarse Gain 1Ch 07h R/W
Fine Offset LSBs 1Dh 00h R/W
Blue Coarse Offset 1Eh 10h R/W
Green Coarse Offset 1Fh 10h R/W
Red Coarse Offset 20h 10h R/W
HSOUT Output Start 21h 0Dh R/W
MISC Control 4 22h 08h R/W
Blue Digital ALC Output LSBs 23h R
Green Digital ALC Output LSBs 24h R
(1) For proper operation of the TVP7002 device, the default settings for all register locations designated as "Reserved" in the register map
summary should never be changed from the values provided.
(2) For registers with reserved bits, a 0b must be written to reserved bit locations, unless otherwise stated.
(3) R = Read only, W = Write only, R/W = Read/Write
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