Datasheet

TVP7002
SLES206C –MAY 2007–REVISED APRIL 2013 www.ti.com
Electrical Characteristics
IOVDD = 3.3 V, DVDD = 1.9 V, PLL_AVDD = 1.9 V, AVDD = 1.9 V, A33VDD = 3.3 V, T
A
= 0°C to 70°C (unless otherwise
noted)
PARAMETER TEST CONDITIONS
(1)
MIN TYP MAX UNIT
Analog Interface
Input voltage range By design 0.5 1 2 V
pp
Z
I
Input impedance, analog video inputs By design 500 kΩ
Digital Logic Interface
C
I
Input capacitance By design 10 pF
Z
I
Input impedance By design 500 kΩ
V
OH
Output voltage high I
OH
= 2 mA 0.8 IOVDD V
V
OL
Output voltage low I
OL
= –2 mA 0.2 IOVDD V
V
OH_SCLK
DATACLK output voltage high I
OH
= 4 mA 0.8 IOVDD V
V
OL_SCLK
DATACLK output voltage low I
OH
= –4 mA 0.2 IOVDD V
V
IH
High-level input voltage By design 0.7 IOVDD V
V
IL
Low-level input voltage By design 0.3 IOVDD V
ADCs
ADC full-scale input range Clamp disabled 0.95 1 1.05 V
pp
ADC resolution 10-bit range 10 bits
10 bit, 110 MHz, BC = 5 –1 ±0.5 +1
DNL DC differential nonlinearity LSB
8 bit, 162 MHz, BC = 8 –1 ±0.5 +1
10 bit, 110 MHz, BC = 5 –4 ±1 +4
INL DC integral nonlinearity LSB
8 bit, 162 MHz, BC = 8 –4 ±1 +4
10 bit, 110 MHz, BC = 5 none
Missing code
8 bit, 162 MHz, BC = 8 none
SNR Signal-to-noise ratio 10 MHz, 1 V
P-P
at 110 MSPS 55 dB
Analog 3-dB bandwidth By design 350 500 MHz
Horizontal PLL
Clock jitter 500 ps
Phase adjustment 11.6 degree
VCO frequency range By design 12 162 MHz
Analog ADC Channel
Coarse gain full-scale control range Gain control value N
G
= 15 ±6 dB
Coarse offset full-scale control range Referred to 10-bit ADC output ±124 counts
Coarse offset step size Referred to 10-bit ADC output 4 counts
Sync Processing
Internal clock reference frequency By design 6.5 MHz
(1) BC = ADC bias control setting in I
2
C register, 2Ch
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