Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsLogic ICsLogic IC - Transducer Converter, Bidirectional US 8

YZP PACKAGE

(BOTTOM VIEW)

GND

CCA

CCB

CCA

GND

DCT OR DCU PACKAGE

(TOP VIEW)

D1 D2

TXB0102

www.ti.com

SCES641B –MAY 2007–REVISED MAY 2012

2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR

WITH AUTO DIRECTION SENSING AND ±15-kV ESD PROTECTION

Check for Samples: TXB0102

FEATURES

• Latch-Up Performance Exceeds 100 mA Per

JESD 78, Class II

• Available in the Texas Instruments NanoFree™

• ESD Protection Exceeds JESD 22

Packages

– A Port

• 1.2 V to 3.6 V on A Port and 1.65 V to 5.5 V on

B Port (V

CCA

≤ V

CCB

)

– 2500-V Human-Body Model (A114-B)

• V

Isolation Feature – If Either V

Input Is at

– 200-V Machine Model (A115-A)

GND, All Outputs Are in the High-Impedance

– 1500-V Charged-Device Model (C101)

State

– B Port

• OE Input Circuit Referenced to V

CCA

– 15-kV Human-Body Model (A114-B)

• Low Power Consumption, 4-μA Max I

– 200-V Machine Model (A115-A)

• I

off

Supports Partial-Power-Down Mode

– 1500-V Charged-Device Model (C101)

Operation

A. Pull up resistors are not required on both sides for Logic I/O.

B. If pull up or pull down resistors are needed, the resistor value must be over 50 kΩ.

C. 50 kΩ is a safe recommended value, if the customer can accept higher Vol or lower Voh, smaller pull up or pull down

resistor is allowed, the draft estimation is Vol = Vccout × 4.5k/(4.5k + Rpu) and Voh = Vccout × Rdw/(4.5k + Rdw).

D. If pull up resistors are needed, please refer to the TXS0102 or contact TI.

E. For detailed information, please refer to application note SCEA043.

DESCRIPTION/ORDERING INFORMATION

This 2-bit non-inverting translator uses two separate configurable power-supply rails. The A port is designed to

track V

CCA

. V

CCA

accepts any supply voltage from 1.2 V to 3.6 V. The B port is designed to track V

CCB

. V

CCB

accepts any supply voltage from 1.65 V to 5.5 V. This allows for universal low-voltage bidirectional translation

between any of the 1.2-V, 1.5-V, 1.8-V, 2.5-V, 3.3-V, and 5-V voltage nodes. V

CCA

should not exceed V

CCB

When the output-enable (OE) input is low, all outputs are placed in the high-impedance state.

This device is fully specified for partial-power-down applications using I

off

. The I

off

circuitry disables the outputs,

preventing damaging current backflow through the device when it is powered down.

To ensure the high-impedance state during power up or power down, OE should be tied to GND through a

pulldown resistor; the minimum value of the resistor is determined by the current-sourcing capability of the driver.

NanoFree™ package technology is a major breakthrough in IC packaging concepts, using the die as the

package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2NanoFree is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (20 pages)

PAGE 1
TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 2-BIT BIDIRECTIONAL VOLTAGE-LEVEL TRANSLATOR WITH AUTO DIRECTION SENSING AND ±15-kV ESD PROTECTION Check for Samples: TXB0102 FEATURES • 1 • 2 • • • • • Available in the Texas Instruments NanoFree™ Packages 1.2 V to 3.6 V on A Port and 1.65 V to 5.
PAGE 2
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. ORDERING INFORMATION TA PACKAGE (1) (2) NanoFree™ – WCSP (DSBGA) 0.
PAGE 3
TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 Absolute Maximum Ratings (1) over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT VCCA Supply voltage range –0.5 4.6 VCCB Supply voltage range –0.5 6.5 VI Input voltage range (2) A port –0.5 4.6 B port –0.5 6.5 VO Voltage range applied to any output in the high-impedance or power-off state (2) A port –0.5 4.6 B port –0.5 6.
PAGE 4
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 Electrical Characteristics (1) www.ti.com (2) over recommended operating free-air temperature range (unless otherwise noted) PARAMETER TEST CONDITIONS VCCA TA = 25°C VCCB MIN 1.2 V IOH = –20 μA VOLA IOL = 20 μA VOHB IOH = –20 μA 1.65 V to 5.5 V VOLB IOL = 20 μA 1.65 V to 5.5 V V 0.9 1.4 V to 3.6 V VCCB – 0.4 V 0.4 V μA 1.65 V to 5.5 V ±1 ±2 A port 0V 0 V to 5.5 V ±1 ±2 B port VI or VO = 0 to 5.5 V 0 V to 3.
PAGE 5
TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 Timing Requirements over recommended operating free-air temperature range, VCCA = 1.8 V ± 0.15 V (unless otherwise noted) VCCB = 1.8 V ± 0.15 V MIN MAX Data rate tw VCCB = 2.5 V ± 0.2 V MIN MAX 60 Pulse duration Data inputs VCCB = 3.3 V ± 0.3 V MIN MAX 60 17 VCCB = 5 V ± 0.5 V MIN 60 17 UNIT MAX 60 17 Mbps 17 ns Timing Requirements over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.
PAGE 6
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 www.ti.com Switching Characteristics over recommended operating free-air temperature range, VCCA = 1.5 V ± 0.1 V (unless otherwise noted) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A B ten OE tdis OE VCCB = 1.8 V ± 0.15 V VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V MIN MAX MIN MAX MIN B 1.4 12.9 1.2 10.1 A 0.9 14.2 0.7 12 VCCB = 5 V ± 0.5 V UNIT MAX MIN MAX 1.1 10 0.8 9.9 0.4 11.7 0.3 13.7 A 1 1 1 1 B 1 1 1 1 A 5.
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TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 Switching Characteristics over recommended operating free-air temperature range, VCCA = 2.5 V ± 0.2 V (unless otherwise noted) PARAMETER tpd FROM (INPUT) TO (OUTPUT) A B ten OE tdis OE VCCB = 2.5 V ± 0.2 V VCCB = 3.3 V ± 0.3 V MIN MAX B 1.1 A 1.2 VCCB = 5 V ± 0.5 V UNIT MIN MAX MIN MAX 6.3 1 5.2 0.9 4.7 6.6 1.1 5.1 0.9 4.4 A 1 1 1 B 1 1 1 A 5.1 21.3 4.6 15.2 4.6 13.2 B 4.4 20.8 3.8 16 3.9 13.
PAGE 8
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 www.ti.com Operating Characteristics TA = 25°C VCCA 1.2 V 1.2 V 1.5 V 1.8 V 2.5 V 2.5 V 3.3 V 2.5 V 5V 3.
PAGE 9
TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 PRINCIPLES OF OPERATION Applications The TXB0102 can be used in level-translation applications for interfacing devices or systems operating at different interface voltages with one another. Architecture The TXB0102 architecture (see Figure 2) does not require a direction-control signal to control the direction of data flow from A to B or from B to A.
PAGE 10
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 www.ti.com IIN VT/4 kΩ VIN –(VD – VT)/4 kΩ A. VT is the input threshold voltage of the TXB0102 (typically VCCI/2. B. VD is the supply voltage of the external driver. Figure 3. Typical IIN vs VIN Curve Power Up During operation, ensure that VCCA ≤ VCCB at all times. During power-up sequencing, VCCA ≥ VCCB does not damage the device, so any power supply can be ramped up first.
PAGE 11
TXB0102 www.ti.com SCES641B – MAY 2007 – REVISED MAY 2012 PARAMETER MEASUREMENT INFORMATION 2 × VCCO From Output Under Test 50 kW From Output Under Test 15 pF 15 pF 1 MW Open 50 kW TEST tPZL/tPLZ tPHZ/tPZH LOAD CIRCUIT FOR ENABLE/DISABLE TIME MEASUREMENT LOAD CIRCUIT FOR MAX DATA RATE, PULSE DURATION PROPAGATION DELAY OUTPUT RISE AND FALL TIME MEASUREMENT S1 S1 2 × VCCO Open VCCI Input VCCI/2 VCCI/2 0V tPLH tPHL tw Output VCCO/2 0.9 y VCCO 0.
PAGE 12
TXB0102 SCES641B – MAY 2007 – REVISED MAY 2012 www.ti.com REVISION HISTORY Changes from Original (May 2007) to Revision A • Added ball labels to the YZP Package. ................................................................................................................................ 1 Changes from Revision A (January 2011) to Revision B • 12 Page Page Added notes to pin out graphics. ..............................................................................................................
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PAGE 14
PAGE 15
D: Max = 1.918 mm, Min = 1.858 mm E: Max = 0.918 mm, Min = 0.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.
PAGE 17
PACKAGE OPTION ADDENDUM www.ti.com 17-Nov-2013 (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided.
PAGE 18
PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant TXB0102DCUR US8 DCU 8 3000 180.0 8.4 2.25 3.35 1.05 4.0 8.0 Q3 TXB0102YZPR DSBGA YZP 8 3000 180.0 8.4 1.02 2.02 0.63 4.0 8.0 Q1 TXB0102YZPR DSBGA YZP 8 3000 178.0 9.2 1.02 2.02 0.63 4.0 8.
PAGE 19
PACKAGE MATERIALS INFORMATION www.ti.com 23-Aug-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) TXB0102DCUR US8 DCU 8 3000 202.0 201.0 28.0 TXB0102YZPR DSBGA YZP 8 3000 182.0 182.0 17.0 TXB0102YZPR DSBGA YZP 8 3000 220.0 220.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.