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UC2825A-EP

www.ti.com

SGLS305D –JULY 2005–REVISED SEPTEMBER 2010

HIGH-SPEED PWM CONTROLLER

Check for Samples: UC2825A-EP

FEATURES

• Improved Version of the UC2825 PWM SUPPORTS DEFENSE, AEROSPACE,

AND MEDICAL APPLICATIONS

• Compatible With Voltage-Mode or

• Controlled Baseline

Current-Mode Control Methods

• One Assembly/Test Site

• Practical Operation at Switching Frequencies

• One Fabrication Site

to 1 MHz

• Available in Military (–55°C/125°C)

• 50-ns Propagation Delay to Output

Temperature Range

(1)

• High-Current Dual Totem-Pole Outputs

• Extended Product Life Cycle

(2-A Peak)

• Extended Product-Change Notification

• Trimmed Oscillator Discharge Current

• Product Traceability

• Low 100-mA Startup Current

• Pulse-by-Pulse Current-Limiting Comparator

• Latched Overcurrent Comparator With Full

Cycle Restart (1) Additional temperature ranges are available - contact factory

DESCRIPTION/ORDERING INFORMATION

The UC2825A-EP pulse width modulation (PWM) controller is an improved version of the standard UC2825.

Performance enhancements have been made to several of the circuit blocks. Error amplifier gain bandwidth

product is 12 MHz, while input offset voltage is 2 mV. Current-limit threshold is specified to a tolerance of 5%.

Oscillator discharge current is specified at 10 mA for accurate dead-time control. Frequency accuracy is

improved to 6%. Startup supply current, typically 100 mA, is ideal for off-line applications. The output drivers are

redesigned to actively sink current during undervoltage lockout (UVLO) at no expense to the startup current

specification. In addition, each output is capable of 2-A peak currents during transitions.

Functional improvements also have been implemented in this family. The UC2825A-EP shutdown comparator is

now a high-speed overcurrent comparator with a threshold of 1.2 V. The overcurrent comparator sets a latch that

ensures full discharge of the soft-start capacitor before allowing a restart. While the fault latch is set, the outputs

are in the low state. In the event of continuous faults, the soft-start capacitor is fully charged before discharge to

ensure that the fault frequency does not exceed the designed soft-start period. The UC2825 CLOCK pin is

CLK/LEB in the UC2825A-EP. This pin combines the functions of clock output and leading-edge blanking

adjustment and has been buffered for easier interfacing.

The UC2825A-EP has dual alternating outputs and the same pin configuration as UC2825. UVLO thresholds are

identical to the original UC2825.

Consult the application report, The UC3823A,B and UC2825A,B Enhanced Generation of PWM Controllers,

literature number SLUA125, for detailed technical and applications information.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (21 pages)

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UC2825A-EP www.ti.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 PIN ASSIGNMENTS DW PACKAGE (TOP VIEW) INV NI EAOUT CLK/LEB RT CT RAMP SS 1 16 2 15 3 14 4 13 5 12 6 11 7 10 8 9 VREF VCC OUTB VC PGND OUTA GND ILIM TERMINAL FUNCTIONS TERMINAL NAME NO. I/O DESCRIPTION CLK/LEB 4 O Clock/leading-edge blanking. Output of the internal oscillator. CT 6 I Capacitor timing. Timing capacitor connection for oscillator frequency programming.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com Absolute Maximum Ratings over operating free-air temperature range (unless otherwise noted) (1) UNIT VIN Supply voltage VC, VCC 22 V IO Source or sink current, DC OUTA, OUTB 0.5 A IO Source or sink current, pulse (0.5 ms) OUTA, OUTB 2.2 A INV, NI, RAMP –0.3 V to 7 V ILIM, SS –0.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 Electrical Characteristics TA = –40°C to 125°C for Q temperature and TA = –55°C to 125°C for M temperature, RT = 3.65 kΩ, CT = 1 nF, VCC = 12 V PARAMETER TEST CONDITIONS MIN TYP MAX UNIT 5.05 5.1 5.15 2 15 mV 20 mV Reference, VREF VO Output voltage range TJ = 25°C, IO = 1 mA Line regulation 12 V ≤ VCC ≤ 20 V Load regulation 1 mA ≤ IO ≤ 10 mA Total output variation Line, load, temperature 5 5.03 V 5.17 V 0.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com Electrical Characteristics (continued) TA = –40°C to 125°C for Q temperature and TA = –55°C to 125°C for M temperature, RT = 3.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 APPLICATION INFORMATION The oscillator of the UC2825A-EP is a sawtooth. The rising edge is governed by a current controlled by the RT pin and value of capacitance at the CT pin (CCT). The falling edge of the sawtooth sets dead time for the outputs. Selection of RT should be done first, based on desired maximum duty cycle. CT then can be chosen, based on the desired frequency (RT) and DMAX.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com Leading-Edge Blanking (LEB) The UC2825A-EP performs fixed-frequency PWM control. The UC2825A-EP outputs are alternately controlled. During every other cycle, one output is off. Each output then switches at one-half the oscillator frequency, varying in duty cycle from 0 to less than 50%. To limit maximum duty cycle, the internal clock pulse blanks both outputs low during the discharge time of the oscillator.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 Undervoltage Lockout (UVLO), Soft-Start, and Fault Management Soft-start is programmed by a capacitor on the soft-start (SS) pin. At power up, SS is discharged. When SS is low, the error-amplifier output also is forced low. While the internal 9-mA source charges SS, the error-amplifier output follows until closed-loop regulation takes over. Anytime ILIM exceeds 1.2 V, the fault latch is set and the output pins are driven low.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com Active-Low Outputs During UVLO The UVLO function forces the outputs to be low and considers both VCC and VREF before allowing the chip to operate. 3 –555C VOUT – V 2 255C 1 VCC = OPEN 0 0 0.2 0.4 0.6 0.8 1.0 Current – A UDG−95108 Figure 6. Output Voltage vs Output Current VCC 250 mA OUT 50 k UVLO Q2 Q1 Q3 Q4 PGND UDG−95106 Figure 7.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 Synchronization The oscillator can be synchronized by an external pulse inserted in series with the timing capacitor. Program the free-running frequency of the oscillator to be 10% to 15% slower than the desired synchronous frequency. The pulse width should be greater than 10 ns and less than half the discharge time of the oscillator. The rising edge of the CLK/LEB pin can be used to generate a synchronizing pulse for other chips.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com High-Current Outputs Each totem-pole output of the UC2825A-EP can deliver a 2-A peak current into a capacitive load. The output can slew a 1000-pF capacitor by 15 V in approximately 20 ns. Separate collector supply (VC) and power ground (PGND) pins help decouple the device analog circuitry from the high-power gate drive noise.
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UC2825A-EP www.ti.com SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 Ground Planes Each output driver of these devices is capable of 2-A peak currents. Careful layout is essential for correct operation of the chip. A ground plane must be employed. A unique section of the ground plane must be designated for high di/dt currents associated with the output stages. This point is the power ground to which the PGND pin is connected.
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UC2825A-EP SGLS305D – JULY 2005 – REVISED SEPTEMBER 2010 www.ti.com Open-Loop Test Circuit This test fixture is useful for exercising many functions of this device family and measuring their specifications. As with any wideband circuit, careful grounding and bypass procedures should be followed. The use of a ground plane is highly recommended. UC2825A-EP CLK/LEB CLEB 3.65 kW CT RT 1 mF VCC 0.1 mF 15 V 10 mF Oscillator CT 15 V 10 mF VC 0.1 mF RAMP OUTA EAOUT 50 W 22 kW 27 kW 4.
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PACKAGE OPTION ADDENDUM www.ti.
PAGE 16
PACKAGE OPTION ADDENDUM www.ti.com 31-Aug-2010 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC2825AMDWREP Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.85 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.8 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2825AMDWREP SOIC DW 16 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46C and to discontinue any product or service per JESD48B. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.