Datasheet

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CL SS

VREF

CS−

CS+

EA+

EA−

COMP

SHUTDOWN

VIN

BOUT

GND

AOUT

SYNC

DW PACKAGE

(TOP VIEW)

P0008-01

UC2856Q

www.ti.com

SGLS265A –NOVEMBER 2004– REVISED MAY 2011

IMPROVED CURRENT MODE PWM CONTROLLER

Check for Samples: UC2856Q

FEATURES

• Pin-for-Pin Compatible With the UC2846

• 65-ns Typical Delay From Shutdown to

Outputs and 50-ns Typical Delay From

Sync to Outputs

• Improved Current Sense Amplifier With

Reduced Noise Sensitivity

• Differential Current Sense With 3-V

Common Mode Range

• Trimmed Oscillator Discharge Current for

Accurate Deadband Control

• Accurate 1-V Shutdown Threshold

• High Current Dual Totem Pole

Outputs (1.5-A peak)

• TTL Compatible Oscillator SYNC Pin

Thresholds

• 4-kV ESD Protection

DESCRIPTION

The UC2856 is a high performance version of the popular UC2846 series of current mode controllers, and is

intended for both design upgrades and new applications where speed and accuracy are important. All input to

output delays have been minimized, and the current sense output is slew rate limited to reduce noise sensitivity.

Fast 1.5-A peak output stages have been added to allow rapid switching of power FETs.

A low impedance TTL compatible sync output has been implemented with a 3-state function when used as a

sync input.

Internal chip grounding has been improved to minimize internal noise caused when driving large capacitive

loads. This, in conjunction with the improved differential current sense amplifier, results in enhanced noise

immunity.

Other features include a trimmed oscillator current (8%) for accurate frequency and dead time control; a 1 V, 5%

shutdown threshold; and 4 kV minimum ESD protection on all pins.

ORDERING INFORMATION

(1)

ORDERABLE TOP-SIDE

PACKAGE

PART NUMBER MARKING

–40°C to 125°C SOP–DW Tape and reel UC2856QDWR UC2856Q

(1) Package drawings, standard packing quantities, thermal data, symbolization, and PCB design

guidelines are available at www.ti.com/sc/package.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (15 pages)

PAGE 1
UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.
PAGE 2
UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. BLOCK DIAGRAM 5.1 V Reference Regulator VIN 15 2 VREF SYNC 10 RT UV Lockout 9 13 VC OSC CT 8 FF 11 AOUT Q T 4.1 V CS− 3 − X3 CS+ Q + COMP + 4 R S − Q − S 0.5 V 14 BOUT + 0.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS over operating free-air temperature range (unless otherwise noted) (1) (2) UNIT Supply voltage 40 V Collector supply voltage IO Output current (sink or source) 40 V DC 0.5 A Pulse (0.5 ms) 2A Error amplifier input voltage –0.3 V to VIN Shutdown input voltage –0.3 V to 10 V Current sense input voltage –0.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated)(1) PARAMETER TEST CONDITIONS MIN TYP MAX UNIT ERROR AMPLIFIER SECTION Input offset voltage VCM = 2 V Input bias current Input offset current 5 mV –1 µA 500 nA Common mode range VIN = 8 V to 40 V 0 Open loop gain VO = 1.2 V to 3 V 80 100 dB Unity gain bandwidth TJ = 25°C 1 1.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) TA = –40°C to 125°C, VIN = 15 V, RT = 10 kΩ, CT = 1 nF, and TA = TJ (unless otherwise stated)(1) PARAMETER TEST CONDITIONS MIN TYP MAX 45% 47% 50% UNIT PWM SECTION Maximum duty cycle Minimum duty cycle 0% UNDERVOLTAGE LOCKOUT SECTION Startup threshold 7.7 Threshold hysterisis 0.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com APPLICATION AND OPERATION INFORMATION VREF SAWTOOTH CT 9 COMP OSC SYNC 8 CT RT Output Deadtime (td) 8 mA 10 SYNC NOTE: Output deadtime is determined by the size of the external capacitor, CT, according to the formula: For large values of RT: Td + 250 C T 2 ƒT + Oscillator frequency is approximated by the formula: RT CT Td + 2C T 8 mA * R3.6 T S0019-01 Figure 1. Oscillator Circuit NOTE: Error Amplifier can source up to 0.5 mA.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com 110 VIN = 20 V TJ = 25° Open-Loop Voltage Gain − dB 105 100 95 90 85 RL 80 75 70 0 10 20 30 40 50 60 70 80 90 100 110 RL − Output Load Resistance − kΩ G002 Figure 4.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com IS (+) 4 RS ISENSE (−) X3 COMP 3 − 0.5 V VREF + 0.5 mA R1 EA 1 Current Limit R2 7 COMP S0022-01 ǒ R2 NOTE: Peak current (IS) is determined by the formula: I + S V Ǔ REF * 0.5 R1)R2 3RS Figure 6.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com VREF ISENSE + R1 1 − 0.5 V Current Limit COMP S S ISS C R2 EA VREF 16 SHUTDOWN + − + - 1.0 V SHUTDOWN With Auto-Restart SHUTDOWN Without Auto-Restart (Latched) Current Limit 0.5 V 0 Shutdown On Off PWM S0023-01 NOTE: If VREF / R1 < 0.8 mA, the shutdown latch commutates when ISS = 0.8 mA and a restart cycle will be initiated. If VREF / R1 > 3 mA, the device will latch off until power is recycled. Figure 7.
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UC2856Q SGLS265A – NOVEMBER 2004 – REVISED MAY 2011 www.ti.com REVISION HISTORY Changes from Original (November 2004) to Revision A • 10 Page Changed the polarity of the comparator connected to pin 16 in Figure 7 ............................................................................
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 PACKAGING INFORMATION Orderable Device Status (1) UC2856QDWR ACTIVE Package Type Package Pins Package Drawing Qty SOIC DW 16 2000 Eco Plan Lead/Ball Finish (2) Green (RoHS & no Sb/Br) MSL Peak Temp Op Temp (°C) Top-Side Markings (3) CU NIPDAU Level-1-260C-UNLIM (4) -40 to 125 UC2856Q (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs.
PAGE 12
PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UC2856QDWR Package Package Pins Type Drawing SOIC DW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2000 330.0 16.4 Pack Materials-Page 1 10.75 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 10.7 2.7 12.0 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 2-Nov-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2856QDWR SOIC DW 16 2000 367.0 367.0 38.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.