Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers PWM Low side SOIC 8

INPUT

ENBL

TIMER

REF

TIMER

REF

50ns ±500ns

ENBL

GND

BIAS

1.4V

ENABLE

UC1714

ONLY

4 AUX

PWR

1 VCC

LOGIC

GATES

TIMER

REF

3 GND

UC1714, UC1715, UC2714

UC2715, UC3714, UC3715

www.ti.com

SLUS170B –FEBRUARY 1999–REVISED MAY 2013

Complementary Switch FET Drivers

Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715

FEATURES

DESCRIPTION

These two families of high speed drivers are

• Single Input (PWM and TTL Compatible)

designed to provide drive waveforms for

• High-Current Power FET Driver, 1-A Source

complementary switches. Complementary switch

and 2-A Sink

configurations are commonly used in synchronous

• Auxiliary Output FET Driver, 0.5-A Source and

rectification circuits and active clamp/reset circuits,

which provide zero voltage switching. In order to

1-A Sink

facilitate the soft switching transitions, independently

• Time Delays Between Power and Auxiliary

programmable delays between the two output

Outputs Independently Programmable from 50

waveforms are provided on these drivers. The delay

to 500-ns

pins also have true-zero voltage-sensing capability

• Time Delay or True Zero-Voltage Operation

which allows immediate activation of the

Independently Configurable for Each Output

corresponding switch when zero voltage is applied.

These devices require a PWM-type input to operate

• Switching Frequency to 1 MHz

and interface with commonly available PWM

• Typical 50-ns Propagation Delays

controllers.

• ENBL Pin Activates 220-μA Sleep Mode

In the UC1714 series, the AUX output is inverted to

• Power Output is Active-Low in Sleep Mode

allow driving a p-channel MOSFET. In the UC1715

• Synchronous Rectifier Driver

series, the two outputs are configured in a true

complementary fashion.

BLOCK DIAGRAM

Pin numbers refer to J, N and D packages.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

UNLESS OTHERWISE NOTED this document contains

PRODUCTION DATA information current as of publication date.

Products conform to specifications per the terms of Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (16 pages)

PAGE 1
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 www.ti.com SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 Complementary Switch FET Drivers Check for Samples: UC1714, UC1715, UC2714, UC2715, UC3714, UC3715 FEATURES DESCRIPTION • • These two families of high speed drivers are designed to provide drive waveforms for complementary switches. Complementary switch configurations are commonly used in synchronous rectification circuits and active clamp/reset circuits, which provide zero voltage switching.
PAGE 2
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) (2) MIN Auxiliary Driver IOH Auxiliary Driver IOL MAX UNIT continuous –100 mA peak –500 mA 200 mA continuous peak 1 Input Voltage Range (INPUT, ENBL) –0.
PAGE 3
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 www.ti.
PAGE 4
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 www.ti.com PIN DESCRIPTIONS AUX The AUX switches immediately at the rising edge of INPUT’but waits through the T2 delay after the falling edge of INPUT before switching. AUX is capable of sourcing 0.5 A and sinking 1 A of drive current. See the Time Relationships diagram below (Figure 1) for the differences between the UC1714 and UC1715 for INPUT, MAIN, and AUX.
PAGE 5
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 www.ti.com SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 TYPICAL CHARACTERISTICS T1 DELAY, T2 DELAY vs RT TIME RELATIONSHIPS INPUT PROPAGATION DELAYS PWR OUTPUT T1 DELAY T2 DELAY UC1714 AUX OUTPUT UC1715 AUX OUTPUT (2) T1 delay is defined from the 50% point of the transition edge of AUX to the 10% of the rising edge of PWR. T2 delay is defined from the 90% of the falling edge of PWR to the 50% point of the transition edge of AUX. Figure 1. Figure 2.
PAGE 6
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 6 T1 DEADBAND vs TEMPERATURE AUX TO PWR T2 DEADBAND vs TEMPERATURE PWR TO AUX Figure 5. Figure 6.
PAGE 7
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 www.ti.com SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 TYPICAL APPLICATIONS Figure 7. Typical Application With Timed Delays Figure 8. Using The Timer Input For Zero-Voltage Sensing Wake-up occurs with the first pulse while turnoff is determined by the (RTO CTO) time constant. Figure 9.
PAGE 8
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 www.ti.com Figure 10. Using The UC1715 As A Complementary Synchronous Rectifier Switch Driver With N-Channel FETs VIN is limited to 10 V as VCC rises to approximately 2VIN. Figure 11. Synchronous Rectifier Application With A Charge Pump To Drive The High-Side N-Channel Buck Switch With active reset provided by the UC1714 driving an N-channel switch (Q1) and a P-channel auxiliary switch (Q2). Figure 12.
PAGE 9
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 www.ti.com SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 Figure 13.
PAGE 10
UC1714, UC1715, UC2714 UC2715, UC3714, UC3715 SLUS170B – FEBRUARY 1999 – REVISED MAY 2013 www.ti.com REVISION HISTORY Changes from Revision A (January 2002) to Revision B Page • Added TI's general Absolute Maximum Ratings table note to end of Absolute Maximum table .......................................... 2 • Changed ENBL ≥ 0.8V to ENBL ≤ 0.8V in PWR pin description ..........................................................................................
PAGE 11
PACKAGE OPTION ADDENDUM www.ti.
PAGE 12
PACKAGE OPTION ADDENDUM www.ti.
PAGE 13
PACKAGE OPTION ADDENDUM www.ti.com 11-Apr-2013 Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above. Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.
PAGE 14
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant UC2714DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC2715DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3714DTR SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 UC3715DTR SOIC D 8 2500 330.0 12.
PAGE 15
PACKAGE MATERIALS INFORMATION www.ti.com 14-Jul-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UC2714DTR SOIC D 8 2500 367.0 367.0 35.0 UC2715DTR SOIC D 8 2500 367.0 367.0 35.0 UC3714DTR SOIC D 8 2500 367.0 367.0 35.0 UC3715DTR SOIC D 8 2500 367.0 367.0 35.
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