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ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting High side, Low side, Sychronous HTSSOP 14

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SLUS486B − AUGUST 2001 − REVISED JULY 2003

    

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FEATURES



Maximizes Efficiency by Minimizing

Body-Diode Conduction and Reverse

Recovery Losses

 Transparent Synchronous Buck Gate Drive

Operation From the Single Ended PWM Input

Signal

 12-V or 5-V Input Operation

 3.3-V Input Operation With Availability of

12-V Bus Bias

 On-Board 6.5-V Gate Drive Regulator

 ±3.3-A TrueDrive Gate Drives for High

Current Delivery at MOSFET Miller

Thresholds

 Automatically Adjusts for Changing

Operating Conditions

 Thermally Enhanced 14-Pin PowerPAD

HTSSOP Package Minimizes Board Area and

Junction Temperature Rise

APPLICATIONS



Non-Isolated Single or Multi-phased

DC-to-DC Converters for Processor Power,

General Computer, Telecom and Datacom

Applications

DESCRIPTION

The UCC27221 and UCC27222 are high-speed

synchronous buck drivers for today’s

high-efficiency, lower-output voltage designs.

Using Predictive Gate Drive (PGD) control

technology, these drivers reduce diode

conduction and reverse recovery losses in the

synchronous rectifier MOSFET(s). The

UCC27221 has an inverted PWM input while the

UCC27222 has a non-inverting PWM input.

Predictive Gate Drive technology uses control

loops which are stabilized internally and are

therefore transparent to the user. These loops use

no external components, so no additional design

is needed to take advantage of the higher

efficiency of these drivers.

This closed loop feedback system detects

body-diode conduction, and adjusts deadtime

delays to minimize the conduction time interval.

This virtually eliminates body-diode conduction

while adjusting for temperature, load- dependent

delays, and for different MOSFETs. Precise gate

timing at the nanosecond level reduces the

reverse recovery time of the synchronous rectifier

MOSFET body-diode, reducing reverse recovery

losses seen in the main (high-side) MOSFET. The

lower junction temperature in the low-side

MOSFET increases product reliability. Since the

power dissipation is minimized, a higher switching

frequency can also be used, allowing for smaller

component sizes.

The UCC27221 and UCC27222 are offered in the

thermally enhanced 14-pin PowerPAD package

with 2°C/W θ

6,8

4,5

GND

VDD

VLO

11,12

9,10

VHI

UCC27222

PWM

GND

FUNCTIONAL APPLICATION DIAGRAM

Note: 12-V input system shown. For 5-V input only systems, see Figure 6.

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Predictive Gate Drive and PowerPAD are trademarks of Texas Instruments Incorporated.

Summary of content (33 pages)

PAGE 1
SLUS486B − AUGUST 2001 − REVISED JULY 2003 FEATURES Maximizes Efficiency by Minimizing APPLICATIONS Non-Isolated Single or Multi-phased Body-Diode Conduction and Reverse Recovery Losses Transparent Synchronous Buck Gate Drive Operation From the Single Ended PWM Input Signal 12-V or 5-V Input Operation 3.3-V Input Operation With Availability of 12-V Bus Bias On-Board 6.5-V Gate Drive Regulator ±3.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 PWP PACKAGE (TOP VIEW) N/C N/C VDD VLO PVLO AGND IN 1 2 3 4 5 6 7 14 13 12 11 10 9 8 VHI G1 SW SWS G2S G2 PGND N/C − No internal connection AVAILABLE OPTIONS PACKAGED DEVICES TA −40 C to 105 C PWM INPUT (IN) PowerPAD HTSSOP−14 (PWP) INVERTING UCC27221PWP NON-INVERTING UCC27222PWP The PWP package is available taped and reeled. Add R suffix to device type (e.g.
PAGE 3
SLUS486B − AUGUST 2001 − REVISED JULY 2003 ELECTRICAL CHARACTERISTICS VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to VLO, TA = −40 C to 105 C for the UCC2722x, TA = TJ (unless otherwise noted) VLO regulator PARAMETER MIN TYP MAX IVLO = 0 mA IVLO = 0 mA 6.2 6.5 6.8 Regulator output voltage VDD = 12 V, VDD = 20 V, 6.2 6.5 6.8 IVLO = 100 mA 6.1 6.5 6.9 Line Regulation VDD = 8.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 ELECTRICAL CHARACTERISTICS VDD = 12-V, 1-µF capacitor from VDD to GND, 1-µF capacitor from VHI to SW, 0.1-µF and 2.2-µF capacitor from PVLO to PGND, PVLO tied to VLO, TA = −40 C to 105 C for the UCC2722x, TA = TJ (unless otherwise noted) G1 main output MIN TYP MAX Sink resistance PARAMETER SW = 0 V, VHI = 6 V, TEST CONDITIONS IN = 0 V, G1 = 0.5 V 0.3 0.9 1.5 Source resistance(2) Source current(1)(2) SW = 0 V, VHI = 6 V, IN = 6.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 TERMINAL FUNCTIONS TERMINAL NAME NO. DESCRIPTION I/O AGND 6 − Analog ground for all internal logic circuitry. AGND and PGND should be tied to the PCB ground plane with vias. G1 13 O High-side gate driver output that swings between SW and VHI. G2 9 O Low-side gate driver output that swings between PGND and PVLO.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION predictive gate drive technique The Predictive Gate Drive technology utilizes a digital feedback system to detect body-diode conduction, and then adjusts the deadtime delays to minimize it. This system virtually eliminates the body-diode conduction time intervals for the synchronous MOSFET, while adjusting for different MOSFETs characteristics, propagation and load dependent delays.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION A typical application circuit for systems with 8.5-V to 20-V input is shown in Figure 3. VIN D1 CIN C2 PWM Input N/C UCC27222 VHI N/C G1 VDD SW VLO SWS PVLO G2S AGND G2 IN R1 Q1 L1 C1 V OUT Q2 Cout PGND GND GND Figure 3. System Application: 8.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION selection of bypass capacitor C1 Bypass capacitors should be selected based upon allowable ripple voltage, usually expressed as a percent of the regulated power supply rail to be bypassed. In all of the UCC27222 application circuits shown herein, C1 provides the bypass for the main (high-side) gate driver. Every time Q1 is switched on, a packet of charge is removed from C1 to charge Q1’s gate to approximately 6.0 V.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION selection of MOSFETs The peak current rating of a driver imposes a limit on the maximum gate charge of the external power MOSFET driven by it. The limit is based on the amount of time needed to deliver or remove the required charge to achieve the desired switching speed during turn-on and turn-off of the external transistor. Hence, there are the families of gate driver circuits with different current ratings.
PAGE 10
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION regulator current and power dissipation The regulator current can be calculated from the dc or average current required by the two gate drivers.
PAGE 11
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION systems with 5-V input only The circuit pictured in Figure 6 starts up from a 5-V input bus and provides a 6.5-V gate drive to the power MOSFETs. This circuit uses a charge pump consisting of D3, D4 and C3 to effectively double the input voltage and apply this to the input of the linear regulator. The regulator then regulates the doubled input voltage to the 6.5-V nominal for VLO.
PAGE 12
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION selecting D2, D3, and D4 Selection of suitable diodes is based upon the conducted peak and average currents. D2 simply provides a path to charge C2 at converter power-up. Virtually any one of the common BAT54 series of Schottky diodes can be used. To select D3 and D4, the peak currents of these two diodes need to be taken into account.
PAGE 13
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION synchronous rectification and predictive delay In a normal buck converter, when the main switch turns off, current is flowing to the load in the inductor. This current cannot be stopped immediately without using infinite voltage. For the current path to flow and maintain voltage levels at a safe level, a rectifier or catch device is used.
PAGE 14
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION comparison between predictive and adaptive gate drive techniques The first synchronous rectifier controllers had a fixed turn-on delay between the two gate drivers. The advantage of this well-known technique is its simplicity. The drawbacks include the need to make the delay times long enough to cover the entire application of the device and the temperature and lot-to-lot variation of the time delay.
PAGE 15
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION adaptive vs. predictive waveforms Figures 9 through 11 illustrate the adaptive (left) vs. predictive (right) switching waveforms. Key comparison regions are denoted with (A), (B), (C), (D), and (E) for the adaptive control waveforms and (A′), (B′), (C′), (D′), and (E′) for the predictive control waveforms. Figures 10 and 11 are close-ups of each transition edge.
PAGE 16
SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION A4 A C B Complementary Gate Drive Waveforms 2 V / div C4 VDS of SR MOSFET Switch 2 V / div B4 Adaptive Drive 20 ns / div Predictive Drive 20 ns / div Figure 10. Close-Up: Turn-Off of Synchronous Rectifier Switch to Turn-On of Main Switch D E Complementary Gate Drive Waveforms 2 V / div VDS of SR MOSFET Switch 2 V / div Adaptive Drive 20 ns / div D4 E4 Predictive Drive 20 ns / div Figure 11.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 APPLICATION INFORMATION EFFICIENCY vs OUTPUT CURRENT EFFICIENCY vs OUTPUT CURRENT 0.5 ADAPTIVE 0.3 86 84 0.2 82 DELTA POWER DISSIPATION 78 0.1 74 0 5 10 15 IOUT − Output Current − A PREDICTIVE 88 0.3 86 ADAPTIVE 84 0.2 82 80 76 0.0 74 20 0.0 0 5 10 15 IOUT − Output Current − A 96 EFFICIENCY vs OUTPUT CURRENT 96 1.2 1.0 ADAPTIVE 86 0.6 DELTA POWER DISSIPATION 82 0.4 80 78 VIN = 5 V VOUT = 1.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 LAYOUT CONSIDERATIONS packaging The UCC27221/2 are only available in TI’s thermally enhanced 14-pin PowerPad package. This package offers exceptional thermal impedance with a junction-to-case rating of 2 C/W. Shown as the crosshatched region in Figure 16, PowerPad includes an exposed leadframe die pad located on the bottom side of the package. Exposed pad dimensions for the PowerPad TSSOP 14-pin package are 69 mils x 56 mils (1.8 mm x 1.4 mm).
PAGE 19
SLUS486B − AUGUST 2001 − REVISED JULY 2003 REFERENCE DESIGN AND EVALUATION MODULE A reference design is discussed in, 12 V to 1.8 V, 20-A High Efficiency Synchronous Buck Converter Using the UCC27222 with Predictive Gate Drive , TI Literature Number SLUU140 and accompanying evaluation module (EVM) SLUP192. The design highlights UCC27222 and its Predictive Gate Drive synchronous buck operation using a simple single ended PWM controller. The schematic is shown in Figure 17. Figure 17.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 TYPICAL CHARACTERISTICS UVLO THRESHOLD vs TEMPERATURE 16 4.2 14 4.1 4.0 IDD: VDD = 12 V, 500 kHz 12 10 8 IDD: VDD = 8.5 V, Static 6 IVLO: VLO = 12 V, Static, 5 V Only Systems UVLO On 3.9 UVLO Threshold − V ISUPPLY − Bias Current − mA BIAS CURRENT vs TEMPERATURE (NO LOAD) 3.8 3.7 UVLO Off 3.6 3.5 4 3.4 2 3.3 0 3.2 −50 −25 0 25 50 75 100 125 −50 −25 50 TA − Temperature − °C Figure 18 Figure 19 6.8 6.8 6.7 6.
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SLUS486B − AUGUST 2001 − REVISED JULY 2003 TYPICAL CHARACTERISTICS DROPOUT VOLTAGE (VDD AT VLO = 6.175 V) vs TEMPERATURE (IVLO = 100 mA) 8.6 8.6 8.4 8.4 VDD − Dropout Voltage − V VDD − Dropout Voltage − V DROPOUT VOLTAGE (VDD AT VLO = 6.175 V) vs OUTPUT CURENT 8.2 8.0 7.8 7.6 8.2 8.0 7.8 7.6 7.4 7.4 7.2 7.2 7.0 7.
PAGE 22
SLUS486B − AUGUST 2001 − REVISED JULY 2003 TYPICAL CHARACTERISTICS PROPAGATION DELAYS vs TEMPERATURE 4.7 120 4.5 100 tPROP − Propagation Delays − ns PGD Step Resolution − ns PREDICTIVE DELAY BIT WEIGHT vs TEMPERATURE 4.3 4.1 3.9 tOFF, G2 80 tOFF, G1 60 40 3.7 20 3.
PAGE 23
SLUS486B − AUGUST 2001 − REVISED JULY 2003 TYPICAL CHARACTERISTICS G1 RISE AND FALL TIMES vs TEMPERATURE (2.2 nF) G2 RISE AND FALL TIMES vs TEMPERATURE (2.
PAGE 24
SLUS486B − AUGUST 2001 − REVISED JULY 2003 TYPICAL CHARACTERISTICS G2 SOURCE RESISTANCE vs TEMPERATURE G2 SINK RESISTANCE vs TEMPERATURE (RDS(on)) 40 40 35 35 30 G2 RSOURCE − Ω G2 RSINK − Ω 30 25 20 15 25 20 15 10 10 5 5 0 0 −50 −25 0 25 50 75 100 125 −50 −25 0 25 50 75 100 125 TA − Ambient Temperature − °C TA − Temperature − °C Figure 34 Figure 35 RELATED PRODUCTS PART NUMBER DESCRIPTION GATE DRIVE PACKAGE TPS2830/1 Fast synchronous buck MOSFET driv
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com 28-Oct-2012 Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) UCC27221PWPR HTSSOP PWP 14 2000 330.0 12.4 UCC27222PWPR HTSSOP PWP 14 2000 330.0 12.4 Pack Materials-Page 1 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 6.9 5.6 1.6 8.0 12.0 Q1 6.9 5.6 1.6 8.0 12.
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PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2012 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27221PWPR HTSSOP PWP 14 2000 367.0 367.0 35.0 UCC27222PWPR HTSSOP PWP 14 2000 367.0 367.0 35.
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