Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting Low side SOIC 8

ENA

INA

GND

INB

ENB

OUTA

VDD

OUTB

UCC27523

Dual Inverting Inputs

ENA

INA

GND

INB

ENB

OUTA

VDD

OUTB

UCC27524

Dual Non-Inverting Inputs

ENA

INA

GND

INB

ENB

OUTA

VDD

OUTB

UCC27525

One Inverting and One

Non-Inverting Input

INA-

INB-

GND

OUTB

INA+

INB+

OUTA

VDD

UCC27526

Dual Input Configuration

UCC27523, UCC27524, UCC27525, UCC27526

www.ti.com

SLUSAQ3F –NOVEMBER 2011–REVISED MAY 2013

Dual 5-A High-Speed Low-Side Gate Driver

Check for Samples: UCC27523, UCC27524, UCC27525, UCC27526

FEATURES

APPLICATIONS

• Industry-Standard Pin Out

• Switch-Mode Power Supplies

• Two Independent Gate-Drive Channels • DC-to-DC Converters

• 5-A Peak Source and Sink-Drive Current • Motor Control, Solar Power

• Independent-Enable Function for Each Output • Gate Drive for Emerging Wide Band-Gap

Power Devices such as GaN

• TTL and CMOS Compatible Logic Threshold

Independent of Supply Voltage

DESCRIPTION

• Hysteretic-Logic Thresholds for High Noise

The UCC2752x family of devices are dual-channel

Immunity

high-speed low-side gate-driver devices capable of

• Inputs and Enable Pin-Voltage Levels Not

effectively driving MOSFET and IGBT power

Restricted by VDD Pin Bias Supply Voltage

switches. Using a design that inherently minimizes

shoot-through current, UCC2752x is capable of

• 4.5 to 18-V Single-Supply Range

delivering high-peak current pulses of up to 5-A

• Outputs Held Low During VDD-UVLO, (ensures

source and 5-A sink into capacitive loads along with

glitch-free operation at power-up and power-

rail-to-rail drive capability and extremely small

down)

propagation delay typically 13 ns. In addition, the

• Fast Propagation Delays (13-ns typical)

drivers feature matched internal propagation delays

between the two channels which are very well suited

• Fast Rise and Fall Times (7-ns and 6-ns

for applications requiring dual-gate drives with critical

typical)

timing, such as synchronous rectifiers. This also

• 1-ns Typical Delay Matching Between 2-

enables connecting two channels in parallel to

Channels

effectively increase current-drive capability or driving

• Two Outputs are Paralleled for Higher Drive

two switches in parallel with a single input signal. The

input pin thresholds are based on TTL and CMOS

Current

compatible low-voltage logic, which is fixed and

• Outputs Held in LOW When Inputs Floating

independent of the VDD supply voltage. Wide

• PDIP-8, SOIC-8, MSOP-8 PowerPAD™ and 3-

hysteresis between the high and low thresholds offers

mm × 3-mm WSON-8 Package Options

excellent noise immunity.

• Operating Temperature Range of –40°C to

+140°C

PRODUCT MATRIX

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2PowerPAD is a trademark of Texas Instruments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (41 pages)

PAGE 1
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.
PAGE 2
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 ABSOLUTE MAXIMUM RATINGS (1) (2) over operating free-air temperature range (unless otherwise noted) MIN Supply voltage range OUTA, OUTB voltage MAX UNIT VDD -0.3 to 20.0 DC -0.3 to VDD + 0.3 Repetitive pulse < 200 ns (3) -2.0 to VDD + 0.3 Output continuous source/sink current IOUT_DC Output pulsed source/sink current (0.5 µs) IOUT_pulsed 0.
PAGE 4
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com THERMAL INFORMATION THERMAL METRIC UCC27523, UCC27524, UCC27525 UCC27523, UCC27524, UCC27525 SOIC (D) MSOP (DGN) (1) 8 PINS 8 PINS θJA Junction-to-ambient thermal resistance (2) 130.9 71.8 θJCtop Junction-to-case (top) thermal resistance (3) 80.0 65.6 (4) θJB Junction-to-board thermal resistance 71.4 7.4 ψJT Junction-to-top characterization parameter (5) 21.9 7.
PAGE 5
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 ELECTRICAL CHARACTERISTICS VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,) PARAMETER TEST CONDITION MIN TYP MAX UNITS Bias Currents IDD(off) Startup current, (based on UCC27524 Input configuration) VDD = 3.4 V, INA=VDD, INB=VDD 55 VDD = 3.4 V, INA=GND, INB=GND 25 75 145 TJ = 25°C 3.
PAGE 6
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com ELECTRICAL CHARACTERISTICS (continued) VDD = 12 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND. Currents are positive into, negative out of the specified terminal (unless otherwise noted,) PARAMETER tR Rise time tF TEST CONDITION (3) MIN TYP MAX UNITS CLOAD = 1.8 nF 7 18 Fall time (3) CLOAD = 1.
PAGE 7
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 DEVICE INFORMATION UCC27523,4,5(D,DGN) & UCC27524P (TOP VIEW) UCC2752(3,4,5)DSD (TOP VIEW) ENA 1 8 ENB INA 2 7 OUTA GND 3 6 VDD INB 4 5 OUTB UCC27526 DSD (TOP VIEW) ENA 1 8 ENB INA- 1 8 INA+ INA 2 7 OUTA INB- 2 7 INB+ GND 3 6 VDD GND 3 6 OUTA INB 4 5 OUTB OUTB 4 5 VDD Figure 5.
PAGE 8
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Table 1.
PAGE 9
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 Functional Block Diagrams VDD VDD 200 kW ENA 200 kW 1 8 ENB 7 OUTA 6 VDD 5 OUTB VDD VDD 200 kW INA 2 VDD GND 3 VDD VDD UVLO VDD 200 kW INB 4 UDG-11221 Figure 6. UCC27523 Block Diagram VDD VDD 200 kW ENA 200 kW 1 8 ENB VDD INA OUTA 2 7 400 kW VDD VDD VDD UVLO GND 6 3 VDD INB OUTB 4 5 400 kW Figure 7.
PAGE 10
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com VDD VDD 200 kW ENA 200 kW 1 8 ENB 7 OUTA 6 VDD 5 OUTB VDD VDD 200 kW INA 2 VDD VDD GND UVLO 3 VDD INB 4 400 kW UDG-11223 Figure 8. UCC27525 Block Diagram INA+ 8 VDD 400 kW 5 VDD 6 OUTA 4 OUTB VDD VDD 200 kW INA- 1 VDD GND 3 UVLO INB+ 7 VDD VDD 400 kW 200 kW INB- 2 UDG-11222 Figure 9.
PAGE 11
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 TYPICAL CHARACTERISTICS START-UP CURRENT vs TEMPERATURE OPERATING SUPPLY CURRENT vs TEMPERATURE (Outputs switching) 4 Input=VDD Input=GND Operating Supply Current (mA) Startup Current (mA) 0.14 0.12 0.1 0.08 3.5 3 VDD = 12 V fSW = 500 kHz CL = 500 pF VDD=3.4V 0.06 −50 0 50 Temperature (°C) 100 2.5 −50 150 Figure 11.
PAGE 12
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) OUTPUT PULLUP RESISTANCE vs TEMPERATURE OUTPUT PULLDOWN RESISTANCE vs TEMPERATURE 1 VDD = 12 V IOUT = −10 mA Output Pull−down Resistance (Ω) Output Pull−up Resistance (Ω) 7 6 5 4 3 −50 0 50 Temperature (°C) 100 VDD = 12 V IOUT = 10 mA 0.8 0.6 0.4 0.2 −50 150 Figure 17.
PAGE 13
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 TYPICAL CHARACTERISTICS (continued) OPERATING SUPPLY CURRENT vs FREQUENCY PROPAGATION DELAYS vs SUPPLY VOLTAGE 22 VDD = 4.5 V VDD = 12 V VDD = 15 V 50 Propagation Delays (ns) Operating Supply Current (mA) 60 40 CLOAD = 1.8 nF Both channels switching 30 20 Input to Output On delay Input to Ouptut Off Delay EN to Output On Delay EN to Output Off Delay 18 14 10 10 0 CLOAD = 1.
PAGE 14
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com APPLICATION INFORMATION High-current gate-driver devices are required in switching power applications for a variety of reasons. In order to effect fast switching of power devices and reduce associated switching-power losses, a powerful gate-driver device employs between the PWM output of control devices and the gates of the power semiconductor devices.
PAGE 15
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 UCC27526 INA- 1 INA- INA+ 8 2 INB- INB+ 7 3 GND OUTA 6 INB+ V+ GND GND 4 OUTB VDD 5 GND UDG-11226 Figure 28.
PAGE 16
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Introduction The UCC2752x family of products represent Texas Instruments’ latest generation of dual-channel low-side highspeed gate-driver devices featuring 5-A source/sink current capability, industry best-in-class switching characteristics and a host of other features listed in Table 3 all of which combine to ensure efficient, robust and reliable operation in high-frequency switching power circuits. Table 3.
PAGE 17
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 VDD and Under Voltage Lockout The UCC2752x devices have internal undervoltage-lockout (UVLO) protection feature on the VDD pin supply circuit blocks. When VDD is rising and the level is still below UVLO threshold, this circuit holds the output LOW, regardless of the status of the inputs. The UVLO is typically 4.25 V with 350-mV typical hysteresis.
PAGE 18
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Input Stage The input pins of UCC2752x gate-driver devices are based on a TTL and CMOS compatible input-threshold logic that is independent of the VDD supply voltage. With typically high threshold = 2.1 V and typically low threshold = 1.2 V, the logic level thresholds are conveniently driven with PWM control signals derived from 3.3-V and 5-V digital power-controller devices. Wider hysteresis (typ 0.
PAGE 19
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 Enable Function The enable function is an extremely beneficial feature in gate-driver devices especially for certain applications such as synchronous rectification where the driver outputs disable in light-load conditions to prevent negative current circulation and to improve light-load efficiency.
PAGE 20
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com Output Stage The UCC2752x device output stage features a unique architecture on the pullup structure which delivers the highest peak-source current when it is most needed during the Miller plateau region of the power-switch turnon transition (when the power switch drain or collector voltage experiences dV/dt).
PAGE 21
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 Low Propagation Delays and Tightly Matched Outputs The UCC2752x driver devices feature a best in class, 13-ns (typical) propagation delay between input and output which goes to offer the lowest level of pulse-transmission distortion available in the industry for high frequency switching applications.
PAGE 22
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 22 www.ti.com Figure 34. Turnon Propagation Delay (CL = 1.8 nF, VDD = 12 V) Figure 35. Turnon Rise Time (CL = 1.8 nF, VDD = 12 V) Figure 36. . TurnOff Propagation Delay (CL = 1.8 nF, VDD = 12 V) Figure 37. TurnOff Fall Time (CL = 1.
PAGE 23
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 Drive Current and Power Dissipation The UCC27523/4/5/6 family of drivers are capable of delivering 5-A of current to a MOSFET gate for a period of several-hundred nanoseconds at VDD = 12 V. High peak current is required to turn the device ON quickly. Then, to turn the device OFF, the driver is required to sink a similar amount of current to ground which repeats at the operating frequency of the power device.
PAGE 24
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com The switching load presented by a power MOSFET is converted to an equivalent capacitance by examining the gate charge required to switch the device. This gate charge includes the effects of the input capacitance plus the added charge needed to swing the drain voltage of the power device as it switches between the ON and OFF states.
PAGE 25
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the device package. In order for a gate driver device to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits.
PAGE 26
UCC27523, UCC27524, UCC27525, UCC27526 SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 www.ti.com PCB Layout Proper PCB layout is extremely important in a high-current fast-switching circuit to provide appropriate device operation and design robustness. The UCC27523/4/5/6 family of gate drivers incorporates short propagation delays and powerful output stages capable of delivering large current peaks with very fast rise and fall times at the gate of power MOSFET to facilitate voltage transitions very quickly.
PAGE 27
UCC27523, UCC27524, UCC27525, UCC27526 www.ti.com SLUSAQ3F – NOVEMBER 2011 – REVISED MAY 2013 REVISION HISTORY Changes from Original (November 2011) to Revision A • Page Changed datasheet status to Production Data. .................................................................................................................... 1 Changes from Revision A (November 2011) to Revision B Page • Added note to packaging section, "DSD package is rated MSL level 2". ........................................
PAGE 28
PACKAGE OPTION ADDENDUM www.ti.
PAGE 29
PACKAGE OPTION ADDENDUM www.ti.
PAGE 30
PACKAGE OPTION ADDENDUM www.ti.com 29-May-2013 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
PAGE 31
PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing UCC27523DGNR MSOPPower PAD UCC27523DR UCC27523DSDR SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant DGN 8 2500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1 SOIC D 8 2500 330.0 12.4 6.4 5.2 2.1 8.0 12.0 Q1 SON DSD 8 3000 330.0 12.4 3.3 3.3 1.1 8.0 12.
PAGE 32
PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27523DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27523DR SOIC D 8 2500 367.0 367.0 35.0 UCC27523DSDR SON DSD 8 3000 367.0 367.0 35.0 UCC27523DSDT SON DSD 8 250 210.0 185.0 35.0 UCC27524DGNR MSOP-PowerPAD DGN 8 2500 364.0 364.0 27.0 UCC27524DR SOIC D 8 2500 367.0 367.0 35.
PAGE 33
PAGE 34
PAGE 35
PAGE 36
PAGE 37
PAGE 38
PAGE 39
PAGE 40
PAGE 41
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.