Datasheet

ManualsBrandsTEXAS INSTRUMENTS ManualsPMICsPMIC - gate drivers Non-inverting High OR low side SOT 23 6

GND

OUTL

OUTH 1

4IN+

VDD

IN-

OUT 1

GND

IN-

EN 1

4IN+

EN 1

IN1

OUTL

IN2

OUTH

GND

VDD VDD

VDD

OUT OUT

UCC27531 UCC27533 UCC27536 UCC27537 UCC27538

UCC27531

UCC27533, UCC27536

UCC27537, UCC27538

www.ti.com

SLUSBA7D – DECEMBER 2012–REVISED APRIL 2013

2.5-A and 5-A, 35-V

MAX

VDD FET and IGBT Single-Gate Driver

Check for Samples: UCC27531 , UCC27533, UCC27536 , UCC27537, UCC27538

FEATURES

APPLICATIONS

• Low Cost Gate Driver (offering optimal • Switch-Mode Power Supplies

solution for driving FET and IGBTs)

• DC-to-DC Converters

• Superior Replacement to Discrete Transistor

• Solar Inverters, Motor Control, UPS

Pair Drive (providing easy interface with

• HEV and EV Chargers

controller)

• Home Appliances

• TTL and CMOS Compatible Input Logic

• Renewable Energy Power Conversion

Threshold, (independent of supply voltage)

• SiC FET Converters

• Split Output Options Allow for Tuning of Turn-

On and Turn-Off Currents

DESCRIPTION

• Inverting and Non-Inverting Input

The UCC2753x family of devices are single-channel,

Configurations

high-speed, gate drivers capable of effectively driving

• Enable with Fixed TTL Compatible Threshold

MOSFET and IGBT power switches by up to 2.5-A

source and 5-A sink (asymmetrical drive) peak

• High 2.5-A Source and 2.5-A or 5-A Sink Peak

current. Strong sink capability in asymmetrical drive

Drive Currents at 18-V VDD

boosts immunity against parasitic Miller turn-on effect.

• Wide VDD Range From 10 V up to 35 V

The UCC2753x device can also feature a split-output

• Input and Enable Pins Capable of

configuration where the gate-drive current is sourced

Withstanding up to -5-V DC Below Ground

through OUTH pin and sunk through OUTL pin. This

pin arrangement allows the user to apply independent

• Output Held Low When Inputs are Floating or

turn-on and turn-off resistors to the OUTH and OUTL

During VDD UVLO

pins respectively and easily control the switching slew

• Fast Propagation Delays (17-ns typical)

rates.

• Fast Rise and Fall Times

The driver has rail-to-rail drive capability and

(15-ns and 7-ns typical with 1800-pF Load)

extremely small propagation delay typically 17 ns.

• Under Voltage Lockout (UVLO)

The input threshold of UCC2753xDBV is based on

• Used as a High-Side or Low-Side Driver (if

TTL and CMOS compatible low-voltage logic, which

designed with proper bias and signal isolation)

is fixed and independent of VDD supply voltage. The

• Low Cost, Space Saving 5-Pin or 6-Pin DBV

1-V typical hysteresis offers excellent noise immunity.

(SOT-23) Package Options

The driver has EN pin with fixed TTL compatible

• UCC27536 and UCC27537 Pin-to-Pin

threshold. EN is internally pulled up; pulling EN low

compatible to TPS2828 and TPS2829

disables driver, while leaving it open provides normal

operation. The EN pin can be used as an additional

• Operating Temperature Range of -40°C to

input with the same performance as the IN, IN+, IN1,

140°C

and IN2 pins.

UCC2753x (top view)

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (37 pages)

PAGE 1
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 2.
PAGE 2
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with appropriate precautions. Failure to observe proper handling and installation procedures can cause damage. ESD damage can range from subtle performance degradation to complete device failure.
PAGE 3
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 THERMAL INFORMATION THERMAL METRIC UCC27533, UCC27536, UCC27537 UCC27531, UCC27538 DBV DBV (1) 5 PINS 6 PINS θJA Junction-to-ambient thermal resistance (2) 178.3 178.3 θJCtop Junction-to-case (top) thermal resistance (3) 109.7 109.7 (4) θJB Junction-to-board thermal resistance 28.3 28.3 ψJT Junction-to-top characterization parameter (5) 14.7 14.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com ELECTRICAL CHARACTERISTICS Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition specifications are at 25°C.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 ELECTRICAL CHARACTERISTICS (continued) Unless otherwise noted, VDD = 18 V, TA = TJ = -40°C to 140°C, 1-µF capacitor from VDD to GND, f = 100 kHz. Currents are positive into, negative out of the specified terminal. OUTH and OUTL are tied together for UCC27531/8. Typical condition specifications are at 25°C.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Timing Diagram Figure 1. UCC27531: (OUTPUT = OUTH tied to OUTL) INPUT = IN, (EN = VDD), or INPUT = EN, (IN = VDD) UCC27537: (OUTPUT = OUT) INPUT = IN+, (EN = VDD), or INPUT = EN, (IN+ = VDD) UCC27538: (OUTPUT = OUTH tied to OUTL) INPUT = IN1, (IN2 = VDD), or INPUT = IN2, (IN1 = VDD) High INPUT (IN+ pin) Low High IN- pin Low 90% OUTPUT 10% tD1 t r tD2 tf Figure 2.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION Block Diagram IN VDD 2 VREF EN 1 3 VDD 6 OUTH 5 OUTL VDD GND 4 UVLO Figure 4. UCC27531 (EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, in pull-down resistance to GND = 230 kΩ) IN+ VDD 3 VREF IN- 4 1 VDD 5 OUT VDD GND 2 UVLO Figure 5. UCC27533 (IN- pull-up resistance to VREF = 500 kΩ, VREF = 5.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 EN www.ti.com VDD 1 5 VDD 4 OUT VREF IN+ 3 VDD UVLO GND 2 Figure 7. UCC27537 (EN pull-up resistance to VREF = 500 kΩ, VREF = 5.8 V, IN+ pull-down resistance to GND = 230 kΩ) IN1 IN2 VDD 2 5 1 VDD 6 OUTH 4 OUTL VDD UVLO GND 3 Figure 8.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION Typical Application Diagrams UCC27531 EN OUTH 1 6 IN OUTL + 2 5 VDD GND 3 + – 4 GND Bouncing Up to -6.5 V 18 V ISENSE Controller VCE(sense) VCC + – Figure 9. Driving IGBT Without Negative Bias UCC27531 EN OUTH 1 IN 6 OUTL + 2 5 3 4 VDD + – GND 18 V + – 13 V Figure 10.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com UCC27533 IN4 OUT 5 IN+ + 3 VDD GND 1 + – 2 18 V + – 13 V Figure 11. Single Output Driver E/2 + – Isol. UCC2753x Isol. UCC2753x Controller Isol. UCC2753x Isol. UCC2753x E/2 + – Figure 12.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 DEVICE INFORMATION UCC2753x Product Matrix Table 1. UCC2753x Product Matrix UCC27531 UCC27533 UCC27536 UCC27537 UCC27538 2.5 A ION PEAK 2.5 A 2.5 A 2.5 A 2.5 A IOFF PEAK 5A 5A 2.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TERMINAL FUNCTIONS TERMINAL I/O FUNCTION EN I Enable (Pull EN to GND in order to disable output, pull it high or leave open to enable output) 2 IN I Driver non-inverting input 3 VDD I Bias supply input 4 GND - Ground (all signals are referenced to this node) 5 OUTL O 5-A sink current output of driver 6 OUTH O 2.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.
PAGE 14
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS If not specified, INPUT refers to non-inverting input 12 25 10 Fall Time (ns) Rise Time (ns) 20 15 10 8 6 4 Cload = 1.8nF Cload = 1.8nF 2 5 0 10 20 30 Supply Voltage (V) 0 40 20 30 Supply Voltage (V) Figure 13. Rise Time vs. Supply Voltage 40 C002 Figure 14. Fall Time vs.
PAGE 15
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 30 OUT RISING, IN- 5V to 0V OUT FALLING, IN- 0V to 5V 25 VDD = 10V VDD = 18V VDD = 32V 25 23 Supply Current (mA) IN- Input To Output Propagation Delay (ns) 27 21 19 20 15 10 17 5 15 0 Cload = 1.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 300 IN- = GND, EN = VDD IN1 = IN2 = VDD IN- = VDD, EN = GND IN1 = IN2 = GND 250 UCC27538 Startup Current (µA) UCC27536 Startup Current (µA) 300 200 Vdd = 7V 150 100 250 200 Vdd = 7V 150 100 -50 0 50 100 150 -50 0 Temperature (Ü& 50 100 150 Temperature (Ü& C004 C005 Figure 21.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 2.4 9.6 Turn-On UVLO Rising UVLO Falling 2 Input Threshold (V) 9.2 Vdd UVLO Threshold (V) Turn-Off 2.2 8.8 1.8 1.6 1.4 1.2 8.4 1 8 0.8 -50 0 50 100 -50 150 0 50 7HPSHUDWXUH Û& 100 C007 C008 Figure 25. UVLO Threshold Voltage vs. Temperature Figure 26. Input Threshold vs. Temperature 2.4 2.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 1.2 25 ROH ROL Output Pull-Down Resistance (Ÿ) Output Pull-Up Resistance (Ÿ) 1 20 15 10 0.8 0.6 0.4 Vdd = 18V Vdd = 18V 5 0.2 -50 0 50 100 -50 150 0 7HPSHUDWXUH Û& 50 100 C010 Figure 29. Output Pull-Up Resistance vs. Temperature C011 Figure 30. Output Pull-Down Resistance vs.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 TYPICAL CHARACTERISTICS (continued) If not specified, INPUT refers to non-inverting input 16 30 OUT RISING, IN- 5V to 0V OUT FALLING, IN- 0V to 5V 15 22 Rise Time (ns) IN- Propagation Delay (ns) 26 18 14 13 Vdd = 18V Cload = 1.8nF Vdd = 18V 14 12 10 -50 0 50 100 150 Temperature (Ü& 11 C003 -50 0 50 100 150 7HPSHUDWXUH Û& C014 Figure 33. IN- Input-to-Output Propagation Delay vs.
PAGE 20
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com TYPICAL CHARACTERISTICS (continued) 10 140 8 120 Rise Time (ns) Supply Current (mA) If not specified, INPUT refers to non-inverting input 6 4 100 80 Cload = 10nF fsw = 20kHz 2 60 Cload = 10nF 0 40 0 10 20 30 40 0 10 Supply Voltage (V) 20 30 C016 C017 Figure 37. Operating Supply Current vs. Supply Voltage (output switching) Figure 38. Rise Time vs.
PAGE 21
UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 APPLICATION INFORMATION High-current gate driver devices are required in switching power applications for a variety of reasons. In order to enable fast switching of power devices and reduce associated switching power losses, a powerful gate driver can be employed between the PWM output of controllers or signal isolation devices and the gates of the power semiconductor devices.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Table 2. UCC2753x Features and Benefits FEATURE BENEFIT High source and sink current capability, 2.5 A and 5 A (asymmetrical). High current capability offers flexibility in employing UCC2753x device to drive a variety of power switching devices at varying speeds. Low 17 ns (typ) propagation delay. Extremely low pulse transmission distortion. Wide VDD operating range of 10 V to 32 V.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 Input Stage The input pins of UCC2753x device are based on a TTL and CMOS compatible input threshold logic that is independent of the VDD supply voltage. With typical high threshold = 2 V and typical low threshold = 1 V, the logic level thresholds can be conveniently driven with PWM control signals derived from 3.3-V or 5-V logic.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Output Stage The output stage of the UCC2753x device is illustrated in Figure 42. The UCC2753x device features a unique architecture on the output stage which delivers the highest peak source current when it is most needed during the Miller plateau region of the power switch turn-on transition (when the power switch drain/collector voltage experiences dV/dt).
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 The UCC2753x is capable of delivering 2.5-A source, and up to 5-A sink at VDD = 18 V. Strong sink capability results in a very low pull-down impedance in the driver output stage which boosts immunity against the parasitic Miller turn-on (high slew rate dV/dt turn on) effect that is seen in both IGBT and FET power switches .
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com Power Dissipation Power dissipation of the gate driver has two portions as shown in equation below: PDISS = PDC + PSW (1) The DC portion of the power dissipation is PDC = IQ x VDD where IQ is the quiescent current for the driver.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 www.ti.com SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 Thermal Information The useful range of a driver is greatly affected by the drive power requirements of the load and the thermal characteristics of the package. In order for a gate driver to be useful over a particular temperature range the package must allow for the efficient removal of the heat produced while keeping the junction temperature within rated limits.
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UCC27531 UCC27533, UCC27536 UCC27537, UCC27538 SLUSBA7D – DECEMBER 2012 – REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Original (December 2012) to Revision A • Page Changed Block Diagram. ...................................................................................................................................................... 7 Changes from Revision A (December 2012) to Revision B • Page Added UCC27533, UCC27536, UCC27537 and UCC27538 parts to the datasheet. ................
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.com (3) 7-May-2013 MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) UCC27531DBVR SOT-23 DBV 6 3000 179.0 8.4 B0 (mm) K0 (mm) P1 (mm) W Pin1 (mm) Quadrant 3.2 3.2 1.4 4.0 8.0 Q3 UCC27531DBVT SOT-23 DBV 6 250 179.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3 UCC27533DBVR SOT-23 DBV 5 3000 179.0 8.4 3.2 3.2 1.4 4.0 8.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-May-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC27531DBVR SOT-23 DBV 6 3000 203.0 203.0 35.0 UCC27531DBVT SOT-23 DBV 6 250 203.0 203.0 35.0 UCC27533DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 UCC27533DBVT SOT-23 DBV 5 250 203.0 203.0 35.0 UCC27536DBVR SOT-23 DBV 5 3000 203.0 203.0 35.0 UCC27536DBVT SOT-23 DBV 5 250 203.0 203.0 35.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.