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UCC28060

NATURAL INTERLEAVING FEATURES SYSTEM FEATURES

APPLICATIONS

+–

COMP

VREF

PGND

AGND

VCC

ZCDA

ZCDB

GDA

GDB

VINAC

VSENSE

PWMCNTL

UCC28061

TSET

PHB

HVSEN

EMI

Filter

400VDC

PowerGoodto

downstreamconverter

85-265VAC

InputVoltage(V)

70 120 170 220 270

CapacitorRippleCurrent(A)

P =600W

V =400V

OUT

1-PhaseTM

2-PhaseTMInterleave

1-PhaseCCM

UCC28061

www.ti.com

.............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009

Natural Interleaving™ Transition-Mode PFC Controller With Improved Audible Noise

Immunity

• Improved Audible Noise Performance

• Phase Management Capability

• Soft Start on Overvoltage

• FailSafe OVP with Dual Paths Prevents Output

• Integrated Brownout

Over-Voltage Conditions Caused by

Voltage-Sensing Failures

• Improved Efficiency and Design Flexibility

over Traditional, Single-Phase Continuous

• Sensorless Current Shaping Simplifies Board

Conduction Mode (CCM)

Layout and Improves Efficiency

• Input Filter and Output Capacitor Current

• Inrush Safe Current Limiting:

Cancellation:

– Prevents MOSFET conduction during

– Reduced current ripple for higher system

inrush

reliability and smaller bulk capacitor

– Eliminates reverse recovery events in

– Reduced EMI filter size

output rectifiers

• Enables Use of Low-Cost Diodes without

Extensive Snubber Circuitry

• Improved Light-Load Efficiency

• Improved Transient Response

• Complete System-Level Protection

• 1-A Source/1.8-A Sink Gate Drivers

• 100-W to 800-W Power Supplies

• Gaming

• D to A Set Top Boxes

• Adapters

• LCD, Plasma and DLP™ TVs

• Home Audio Systems

Typical Application Circuit

Ripple Current Reduction

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas

Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

2 DLP is a trademark of Texas Instruments.

3 Natural Interleaving is a trademark of Texas Instuments.

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of the Texas

Instruments standard warranty. Production processing does not

necessarily include testing of all parameters.

Summary of content (35 pages)

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UCC28061 UCC2 8060 www.ti.com ..............................................................................................................................................................
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, –40°C < TJ = TA < +125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted. UCC28061 Input voltage range VCC (2) –0.5 to +21 PWMCNTL –0.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com ..............................................................................................................................................................
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 DEVICE INFORMATION UCC28061D SOIC 16-Pin (D) Top View ZCDB 1 16 ZCDA VSENSE 2 15 VREF TSET 3 14 GDA PHB 4 13 PGND COMP 5 12 VCC AGND 6 11 GDB VINAC 7 10 CS HVSEN 8 9 PWMCNTL TERMINAL FUNCTIONS TERMINAL DESCRIPTION NAME NO.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com TERMINAL FUNCTIONS (continued) TERMINAL NO. I/O PWMCNTL 9 O PWM enable logic output: This open-drain output goes low when HVSEN is within the HVSEN good region and the ZCDA and ZCDB inputs are switching correctly if operating in two-phase mode (see PHB Pin).
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 BLOCK DIAGRAM Overcurrent CS HVSENOV OV TSD OC Burst Operation SinglePhase 10 OC -0.2V/-0.015V + 1.4V + 440ms Delay VINAC STOPA STOPB Brownout 7 Thermal ShutDown TJ 12.6V 10.35V + UV + TSD 160C 7mA 12 VCC 14 GDA 11 GDB 13 PGND 8 HVSEN 24V STOPA 13.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com ..............................................................................................................................................................
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com ..............................................................................................................................................................
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.
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UCC28061 www.ti.com ..............................................................................................................................................................
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com APPLICATION INFORMATION Theory of Operation The UCC28061 contains the control circuits for two boost pulse-width modulation (PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 The on-time factors (KTH, KTHS, KTL, KTLS) and the minimum switching period TMIN are proportional to the time setting resistor RTSET, the resistor from the TSET pin to ground, and they can be calculated by Equation 5 through Equation 6: ms RTSET KTL = ´ 4.0 V 133 kW (5) RTSET TMIN = ´ 2.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com Zero Crossing Detection and Valley Switching In transition-mode PFC circuits, the MOSFET turns on when the boost inductor current crosses 0.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 Over-Current Protection Under certain conditions (such as inrush, brownout recovery, and output overload), the PFC power stage sees large currents. It is critical that the power devices be protected from switching during these conditions.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com Improved Error Amplifier The voltage error amplifier is a transconductance amplifier. Voltage loop compensation is connected from the error amplifier output, COMP, to analog ground, AGND. The recommended compensation network is shown in Figure 26. REF COMP + VSENSE CZ CP 4.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 Open-Loop Protection If the feedback loop is disconnected from the device, a current source internal to the UCC28061 pulls the VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device is disabled.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com DESIGN EXAMPLE An example of the UCC28061 PFC controller in a two-phase transition mode interleaved PFC pre-regulator is shown in Figure 28. Bridge F1 – + D3 16V CIN CF4 L1 CA 2.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 Recommended PCB Device Layout CF4 Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current, allowing the circuit to use smaller and less expensive filters.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com Inductor Selection The boost inductor is selected based on the inductor ripple current requirements at the peak of low line. Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE), as shown in Equation 7.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 HVSENSE The HVSENSE pin programs the PWMCNTL output of the UCC28061. The PWMCNTL open-drain output can be used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts in high impedance and pulls to ground when the HVSENSE increases above 2.5 V.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com Output Capacitor Selection The output capacitor (COUT) is selected based on holdup requirements as shown in Equation 19. POUT 1 300 W 1 2 h 2 fLINE 0.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 Selecting an RS for Peak Current Limiting The UCC28061 peak limit comparator senses the total input current and is used to protect the MOSFETs during inrush and over-load conditions.
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UCC28061 SLUS837A – JUNE 2008 – REVISED JULY 2009 .............................................................................................................................................................. www.ti.com Brownout Protection Resistor RA and RB are selected to activate brownout protection at 75% of the specified minimum operated input voltage. Resistor RA programs the brownout hysteresis comparator, which was selected to provide 21 V of hysteresis.
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UCC28061 www.ti.com .............................................................................................................................................................. SLUS837A – JUNE 2008 – REVISED JULY 2009 Loop Compensation Resistor RZ is sized to attenuate low-frequency ripple to less than 2% of the voltage amplifier output range. This value ensures good power factor and low input current harmonic distortion.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE OPTION ADDENDUM www.ti.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2009 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC28061DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel Diameter Width (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 A0 (mm) B0 (mm) K0 (mm) P1 (mm) 6.5 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
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PACKAGE MATERIALS INFORMATION www.ti.com 29-Apr-2009 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28061DR SOIC D 16 2500 333.2 345.9 28.
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IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.