UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com CONTENTS • • • • • • • Electrical Characteristics 5 Device Information 9 Functional Block Diagram 12 Typical Characteristics 13 Application Information 19 Design Example 33 Additional References 41 DESCRIPTION Optimized for consumer applications concerned with audible noise elimination, this solution extends the advantages of transition mode – high efficiency with low-cost components – to higher power ratings than previously possible.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ABSOLUTE MAXIMUM RATINGS (1) All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted. MIN Continuous input voltage range Continuous input current Peak input current Output current Continuous gate current Junction Temperature, TJ Lead Temperature, TSOL 21 PWMCNTL −0.5 20 COMP (3), PHB, HVSEN (4), VINAC (4), VSENSE (4) −0.5 7 ZCDA, ZCDB −0.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com RECOMMENDED OPERATING CONDITIONS All voltages are with respect to GND, −40°C < TJ = TA < 125°C, currents are positive into and negative out of the specified terminal, unless otherwise noted.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITION MIN TYP MAX UNIT VCC Bias Supply VCCSHUNT VCC shunt voltage (1) IVCC = 10 mA IVCC(ULVO) VCC current, UVLO VCC = 11.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted. PARAMETER TEST CONDITION MIN TYP MAX UNIT Soft Start VSSTHR COMP Soft-Start threshold, falling VSENSE = 1.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ELECTRICAL CHARACTERISTICS (continued) At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ, all voltages are with respect to GND, all outputs unloaded, −40°C < TJ = TA < 125°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com DEVICE INFORMATION UCC28063D SOIC 16-Pin (D) ZCDB 1 16 ZCDA VSENSE 2 15 VREF TSET 3 14 GDA PHB 4 13 PGND COMP 5 12 VCC AGND 6 11 GDB VINAC 7 10 CS HVSEN 8 9 PWMCNTL TERMINAL FUNCTIONS TERMINAL I/O DESCRIPTION NAME NO.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Detailed Pin Description Analog Ground: Connect analog signal bypass capacitors, compensation components, and analog signal returns to this pin. Connect the analog and power grounds at a single point to isolate high-current noise signals of the power components from interference with the low-current analog circuits. Error Amplifier Output: The error amplifier is a transconductance amplifier, so this output is a high-impedance current source.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com PWM-Control Output: This open-drain output goes low when HVSEN is within the HVSEN-good region (HVSEN > 2.5 V), there is no FailSafe OV, and there is no Phase-Fail condition when operating in two-phase mode (see PHB pin). Otherwise, PWMCNTL is high-impedance. Timing Set: PWM on-time programming input. Connect a resistor from TSET to AGND to set the on-time versus COMP voltage and the minimum switching period at the gate-drive outputs.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Functional Block Diagram Overcurrent + 100ns Blanking Open Detection CS_OPEN VINAC BROWNOUT HVSEN_OV UVLO EN OC TSET_FLT CS_OPEN TSD Brownout Detection 7 440ms Delay 50mV R Q STOP_GDA S Q STOP_GDB OC HIGH _OV PHASE_B_OFF 12 VCC UVLO 12.6V / 10.35V + BROWNOUT + 1.4V COMP_DSCHG 6.00V Reg. -0.200 V / -0.015V CS 10 DSCHG _RST 1-PHASE VGD Reg. -0.167 V / -0.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS At VCC = 16 V, AGND = PGND = 0 V, VINAC = 3 V, VSENSE = 6 V, HVSEN = 3 V, PHB = 5 V, RTSET = 133 kΩ; all voltages are with respect to GND, all outputs unloaded, TJ = TA = +25°C, and currents are positive into and negative out of the specified terminal, unless otherwise noted.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) ERROR AMPLIFIER OUTPUT CURRENT vs INPUT VOLTAGE ERROR AMPLIFIER TRANSCONDUCTANCE vs VSENSE 150 300 Soft−start Completed 250 LOW_OV Trigger Transconduction 54 µS 50 gM − Transconductance (µS) ICOMP − Output Current (µA) 100 LOW_OV Clear 0 −50 −100 200 150 100 50 −150 5.0 5.2 5.4 5.6 5.8 6.0 6.2 6.4 VVSENSE − Input Voltage (V) 6.6 6.8 0 5.0 7.0 5.2 5.4 5.6 5.8 6.0 6.2 6.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE RISING vs TIME GATE DRIVE FALLING vs TIME 2.0 GD Source Current: VCC = 20 V VCC = 12 V 6 1.5 1.0 4 0.5 2 0 0 -2 0 50 100 150 200 250 300 10 2.0 GD Sink Current: VCC = 20 V VCC = 12 V 8 6 1.0 4 0.5 -0.5 0 -1.0 -2 0 GD Voltage: VCC = 20 V VCC = 12 V -0.5 -1.0 0 20 40 Time - ns 60 80 100 120 140 Time - ns Figure 13. Figure 14.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) GATE DRIVE OUTPUT HIGH vs VCC GATE DRIVE HIGH VOLTAGE vs TEMPERATURE 15 15 RLOAD = 2.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com TYPICAL CHARACTERISTICS (continued) VARIOUS DELAY TIMES vs TEMPERATURE ZERO CURRENT DETECT CLAMP VOLTAGE vs INPUT CURRENT 1000 3.5 3.0 Brownout Filter Delay 2.5 VZCD − Clamp Voltage (V) Delay Time (ms) 100 Phase−Fail Filter Delay 10 Dropout Filter Delay 1 1.5 1.0 0.5 Restart Time Delay 0.1 −40 2.0 −20 0 20 40 60 80 TJ − Temperature (°C) 0.0 100 −0.5 120 −5 −4 −3 −2 −1 0 1 2 IZCD − Input Current (mA) 3 4 G010 5 G011 Figure 21.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com APPLICATION INFORMATION Principles of Operation The UCC28063 contains the control circuits for two parallel-connected boost pulse-width modulated (PWM) power converters. The boost PWM power converters ramp current in the boost inductors for a time period proportional to the voltage on the error amplifier output.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com On-Time Control, Maximum Frequency Limiting, and Restart Timer Gate-drive on-time varies proportionately with the error-amplifier output voltage by a factor called KT (in units of μs/V), as shown in Equation 3. TON = K T (VCOMP - 125mV ) (3) Where: • VCOMP is the output voltage of the error amplifier and 125 mV is a modulator offset voltage. The maximum output of the error amplifier is limited to 4.95 V.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Distortion Reduction Due to the parasitic resonance between the drain-source capacitance of the switching MOSFET and the boost inductor, conventional transition-mode PFC circuits may not be able to absorb power from the input line when the input voltage is near zero. This limitation increases total harmonic distortion as a result of ac-line current waveform distortion in the form of flat spots.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Phase Management and Light-Load Operation Under light-load conditions, switching losses may dominate over conduction losses and efficiency may be improved if one phase (channel) is turned off. At a certain power level, the reduction of switching losses is greater than the increase in conduction losses. Turning off one phase at light load is especially valuable for meeting light-load efficiency standards.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Improved Error Amplifier The voltage-error amplifier is a transconductance amplifier. Voltage-loop compensation is connected from the error amplifier output, COMP, to analog ground, AGND. The recommended Type-II compensation network is shown in Figure 27. For loop-stability purposes, the compensation network values are calculated based on small-signal perturbations of the output voltage using the nominal transconductance (gain) of 55 μS.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Soft Start Soft-start is a process for boosting the output voltage of the PFC converter from the peak of the ac-line input voltage to the desired regulation voltage under controlled conditions. Instead of a dedicated soft-start pin, the UCC28063 uses the voltage error amplifier as a controlled current source to increase the PWM duty-cycle by way of increasing the COMP voltage.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com OVERSHOOT V VSENSEREG VENDofSS VSENSE VCOMPCLMP COMP VSSTHR t I AC-LINE ICOMP ISS,SLOW ISS,FAST HIGH GAIN ENABLED SOFTSTART Figure 30.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Brownout Protection As the power line RMS voltage decreases, RMS input current must increase to maintain a constant output voltage for a specific load. Brownout protection helps prevent excess system thermal stress (due to the higher RMS input current) from exceeding a safe operating level. Power-line voltage is sensed at VINAC.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Dropout Detection It is often the case that the ac-line voltage momentarily drops to zero or nearly zero, due to transient abnormal events affecting the local ac power distribution network. Referred to as ac-line dropouts (or sometimes as line-dips) the duration of such events usually extends to only 1 or 2 line cycles.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com VSENSE COMP IBOHYS ON VINAC VBOCLR VBODET 0V t BROWNOUT DETECT BROWNOUT t BODLY Figure 31. AC-Line Brownout Timing with Illustrative System Behavior VSENSE VINAC COMP VDOCLR VDODET 0V t DROPOUT tDODLY Figure 32.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com VREF VREF is an output which supplies a well-regulated reference voltage to circuits within the device as well as serving as a limited source for external circuits. This output must be bypassed to GND with a low-impedance 0.1-μF or larger capacitor placed as close to the VREF and GND pins as possible. Current draw by external circuits should not exceed a few milli-amperes and should not be pulsing.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com SYSTEM LEVEL PROTECTIONS FailSafe OVP - Output Over-Voltage Protection FailSafe OVP prevents any single failure from allowing the output to boost above safe levels. Redundant paths for output voltage sensing provide additional protection against output over-voltage. Over-voltage protection is implemented through two independent paths: VSENSE and HVSEN. The converter shuts down if either input senses a severe over-voltage condition.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Open-Loop Protection If the feedback loop is disconnected from the device, a 100-nA current source internal to the UCC28063 pulls the VSENSE pin voltage towards ground. When VSENSE falls below 1.20 V, the device becomes disabled. When disabled, the bias supply current decreases, both gate-drive outputs and COMP are actively pulled low, and a soft-start condition is initiated. The device is re-enabled when VSENSE rises above 1.25 V.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Fault Logic Diagram Figure 33 depicts the fault-handling logic involving VSENSE, COMP, and several internal states. PHASE_B_OFF STOP GDB OC STOP GDA HIGH _OV BROWNOUT HVSEN_OV UVLO EN TSET_FLT CS_OPEN TSD HIGH_OV Latch S Q 6.67V COMP Discharge Latch S Q + R R Q Q LOW _OV Latch S Q 6.48V + + 20mV 6.36V R + Q OV-Clear COMP 4μA 2kΩ 1.25V EN + LOW_OV DIS _EA DROPOUT Gain -Disable Latch S Q VCC DIS _High_Gain + R 5.9V VSENSE Q + 3.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com DESIGN EXAMPLE An example of the UCC28063 PFC controller in a two-phase interleaved, transition-mode PFC pre-regulator is shown in Figure 34. Bridge + D3 CIN – RS 12V CA R 100 F1 RZA 2.2uF CF1 1 nF RP 50 k VCC RG1 5 RZB UCC28063 VREF CB 2.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Recommended PCB Device Layout CF4 Interleaved transition-mode PFC system architecture dramatically reduces input and output ripple current, allowing the circuit to use smaller and less expensive filters. To maximize the benefits of interleaving, the input and output filter capacitors should be located after the two phase currents are combined together.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Inductor Selection The boost inductor is selected based on the inductor ripple current requirements at the peak of low line. Selecting the inductor requires calculating the boost converter duty cycle at the peak of low line (DPEAK_LOW_LINE), as shown in Equation 18. DPEAK _ LOW _ LINE = VOUT - VIN_MIN 2 VOUT = 390 V - 85 V 2 » 0.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com HVSENSE The HVSENSE pin programs the PWMCNTL output of the UCC28063. The PWMCNTL open-drain output can be used to disable a downstream converter while the PFC output capacitor is charging. PWMCNTL starts high impedance and pulls to ground when HVSEN increases above 2.5 V. Setting the point where PWMCNTL becomes active requires a voltage divider from the boost voltage to the HVSEN pin to ground.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Output Capacitor Selection The output capacitor (COUT) is selected based on holdup requirements, as shown in Equation 31. POUT 1 300 W 1 2 h fLINE 0.92 47Hz ³ = » 156 mF 2 2 VOUT - (VOUT _ MIN ) 390 V 2 - (252 V)2 2 COUT (31) Two 100-μF capacitors were used in parallel for the output capacitor.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Selecting (RS) for Peak Current Limiting The UCC28063 peak limit comparator senses the total input current and is used to protect the MOSFETs during inrush and over-load conditions. For reliability, the peak current limit (IPEAK) threshold in this design is set for 120% of the nominal maximum current that will be observed during power up, as shown in Equation 37. IPEAK = 2POUT 2(1.2) 2 ´ 300 W 2 ´ 1.2 = » 13 A h ´ VIN _ MIN 0.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Brownout Protection Resistor RA and RB are selected to activate brownout protection at ~75% of the specified minimum-operating input voltage. Resistor RA programs the brownout hysteresis comparator, which is selected to provide 17 V (~12 VRMS) of hysteresis. Calculations for RA and RB are shown in Equation 44 through Equation 47. Hysteresis 17 V RA = = = 8.5MW 2 mA 2 mA (44) To meet voltage requirements, three 2.87-MΩ resistors were used in series for RA.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com Programming VOUT Resistor RC is selected to minimize loading on the power line when the PFC is disabled. Construct resistor RC from two or more resistors in series to meet high-voltage requirements. Resistor RD is then calculated based on RC, the reference voltage, VREF, and the required output voltage, VOUT. Based on the values shown in Equation 51 to Equation 54, the primary output over-voltage protection threshold should be as shown in Equation 55: RC = 2.
UCC28063 SLUSAO7 – SEPTEMBER 2011 www.ti.com ADDITIONAL REFERENCES Related Parts Table 3 lists several TI parts that have characteristics similar to the UCC28063. Table 3.
PACKAGE OPTION ADDENDUM www.ti.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 TAPE AND REEL INFORMATION *All dimensions are nominal Device UCC28063DR Package Package Pins Type Drawing SOIC D 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 16.4 Pack Materials-Page 1 6.5 B0 (mm) K0 (mm) P1 (mm) 10.3 2.1 8.0 W Pin1 (mm) Quadrant 16.
PACKAGE MATERIALS INFORMATION www.ti.com 26-Jan-2013 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) UCC28063DR SOIC D 16 2500 333.2 345.9 28.
IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
